[coreboot-gerrit] [XL] Change in coreboot[master]: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support

[Johnny Lin (Code Review)]

Attention is currently required from: Simon Chou, TimLiu-SMCI, Jonathan Zhang, Christian Walter, Arthur Heymans, Jian-Ming Wang, Shelly Chang.

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71958 )

Change subject: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support
......................................................................

Patch Set 7:

(2 comments)

Patchset:

PS2:
> > With newer xeon_sp processors, the concept of "north bridge" became obsolete, instead uncore shoul […]

Upload patchset 7 for review.

File src/soc/intel/xeon_sp/uncore_acpi.c:

https://review.coreboot.org/c/coreboot/+/71958/comment/6f4847ce_4e9759b1 
PS2, Line 52: static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem)
            : {
            : 	const struct SystemMemoryMapHob *memory_map;
            : 	unsigned int mmap_index;
            : 
            : 	memory_map = get_system_memory_map();
            : 	assert(memory_map != NULL);
            : 	printk(BIOS_DEBUG, "memory_map: %p\n", memory_map);
            : 
            : 	mmap_index = 0;
            : 	for (int e = 0; e < memory_map->numberEntries; ++e) {
            : 		const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e];
            : 		uint64_t addr =
            : 			(uint64_t) ((uint64_t)mem_element->BaseAddress <<
            : 				MEM_ADDR_64MB_SHIFT_BITS);
            : 		uint64_t size =
            : 			(uint64_t) ((uint64_t)mem_element->ElementSize <<
            : 				MEM_ADDR_64MB_SHIFT_BITS);
            : 
            : 		printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, "
            : 			"ElementSize: 0x%x, type: %d, reserved: %d\n",
            : 			e, addr, mem_element->BaseAddress, size,
            : 			mem_element->ElementSize, mem_element->Type,
            : 			(mem_element->Type & MEM_TYPE_RESERVED));
            : 
            : 		assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT);
            : 
            : 		/* skip reserved memory region */
            : 		if (mem_element->Type & MEM_TYPE_RESERVED)
            : 			continue;
            : 
            : 		/* Skip all non processor attached memory regions */
            : 		/* In other words, skip all the types >= MemTypeCxlAccVolatileMem */
            : 		if (mem_element->Type >= MemTypeCxlAccVolatileMem)
            : 			continue;
            : 
            : 		/* skip if this address is already added */
            : 		bool skip = false;
            : 		for (int idx = 0; idx < mmap_index; ++idx) {
            : 			uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) +
            : 				srat_mem[idx].base_address_low;
            : 			if (addr == base_addr) {
            : 				skip = true;
            : 				break;
            : 			}
            : 		}
            : 		if (skip)
            : 			continue;
            : 
            : 		srat_mem[mmap_index].type = 1; /* Memory affinity structure */
            : 		srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t);
            : 		srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff);
            : 		srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32);
            : 		srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff);
            : 		srat_mem[mmap_index].length_high = (uint32_t) (size >> 32);
            : 		srat_mem[mmap_index].proximity_domain = mem_element->SocketId;
            : 		srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED;
            : 		if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0)
            : 			srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE;
            : 		++mmap_index;
            : 	}
            : 
            : 	return mmap_index;
            : }
> exactly the same as nb_acpi. […]

Done