[coreboot-gerrit] Change in coreboot[master]: qcs405: Add 500 ms delay

[Nitheesh Sekar (Code Review)]

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34931 )

Change subject: qcs405: Add 500 ms delay
......................................................................

qcs405: Add 500 ms delay

Add 500 ms delay before writing the ddr training data
to the spi flash. Actual delay has to be calculated based
on the calibrations taken during waveforms.

Change-Id: Ic956d73ad39481beadc0f3496c2f643b12694702
Signed-off-by: Nitheesh Sekar 
---
M src/soc/qualcomm/common/qclib.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/34931/1

diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index ac80a76..f8be4f3 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -16,6 +16,7 @@
 #include <console/cbmem_console.h>
 #include <cbmem.h>
 #include <boardid.h>
+#include <delay.h>
 #include <string.h>
 #include <fmap.h>
 #include <assert.h>
@@ -82,6 +83,8 @@
    } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name,
    		sizeof(te->name))) {

+		mdelay(500); //Add 500 ms delay
+
    	assert(fmap_overwrite_area(QCLIB_FR_DDR_TRAINING_DATA,
    		(const void *)te->blob_address, te->size));