Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38222 )
Change subject: soc/amd/stoneyridge: move to using smbus_host.h definitions ......................................................................
soc/amd/stoneyridge: move to using smbus_host.h definitions
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h.
Change-Id: Ic912b91daf79ecd2c276a383edcda563891cf643 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/38222 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- D src/soc/amd/stoneyridge/include/soc/smbus.h M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/smbus.c M src/soc/amd/stoneyridge/smbus_spd.c M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 13 insertions(+), 41 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h deleted file mode 100644 index ada7cfb..0000000 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __STONEYRIDGE_SMBUS_H__ -#define __STONEYRIDGE_SMBUS_H__ - -#include <stdint.h> -#include <soc/iomap.h> - -int do_smbus_read_byte(u32 mmio, u8 device, u8 address); -int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val); -int do_smbus_recv_byte(u32 mmio, u8 device); -int do_smbus_send_byte(u32 mmio, u8 device, u8 val); - -#endif /* __STONEYRIDGE_SMBUS_H__ */ diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 2dba0d7..6ecf1cd 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -17,10 +17,10 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/smbus.h> +#include <device/smbus_host.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> #include <soc/southbridge.h> -#include <soc/smbus.h>
/* * The southbridge enables all USB controllers by default in SMBUS Control. diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index f5a9d60..5474c5c 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -15,8 +15,8 @@
#include <stdint.h> #include <console/console.h> +#include <device/smbus_host.h> #include <amdblocks/acpimmio.h> -#include <soc/smbus.h> #include <soc/southbridge.h>
/* @@ -25,7 +25,7 @@ */ #define SMBUS_TIMEOUT (100 * 1000 * 10)
-static u8 controller_read8(u32 base, u8 reg) +static u8 controller_read8(uintptr_t base, u8 reg) { switch (base) { case ACPIMMIO_SMBUS_BASE: @@ -33,13 +33,13 @@ case ACPIMMIO_ASF_BASE: return asf_read8(reg); default: - printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n", + printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", base); } return 0xff; }
-static void controller_write8(u32 base, u8 reg, u8 val) +static void controller_write8(uintptr_t base, u8 reg, u8 val) { switch (base) { case ACPIMMIO_SMBUS_BASE: @@ -49,12 +49,12 @@ asf_write8(reg, val); break; default: - printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n", + printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n", base); } }
-static int smbus_wait_until_ready(u32 mmio) +static int smbus_wait_until_ready(uintptr_t mmio) { u32 loops; loops = SMBUS_TIMEOUT; @@ -70,7 +70,7 @@ return -2; /* time out */ }
-static int smbus_wait_until_done(u32 mmio) +static int smbus_wait_until_done(uintptr_t mmio) { u32 loops; loops = SMBUS_TIMEOUT; @@ -89,7 +89,7 @@ return -3; /* timeout */ }
-int do_smbus_recv_byte(u32 mmio, u8 device) +int do_smbus_recv_byte(uintptr_t mmio, u8 device) { u8 byte;
@@ -114,7 +114,7 @@ return byte; }
-int do_smbus_send_byte(u32 mmio, u8 device, u8 val) +int do_smbus_send_byte(uintptr_t mmio, u8 device, u8 val) { u8 byte;
@@ -139,7 +139,7 @@ return 0; }
-int do_smbus_read_byte(u32 mmio, u8 device, u8 address) +int do_smbus_read_byte(uintptr_t mmio, u8 device, u8 address) { u8 byte;
@@ -167,7 +167,7 @@ return byte; }
-int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val) +int do_smbus_write_byte(uintptr_t mmio, u8 device, u8 address, u8 val) { u8 byte;
diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index e57ecde..b588579 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -17,8 +17,8 @@ #include <console/console.h> #include <device/pci_def.h> #include <device/device.h> +#include <device/smbus_host.h> #include <soc/southbridge.h> -#include <soc/smbus.h> #include <amdblocks/dimm_spd.h>
/* diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b0aaf24..7732fc9 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -28,7 +28,6 @@ #include <amdblocks/lpc.h> #include <amdblocks/acpi.h> #include <soc/southbridge.h> -#include <soc/smbus.h> #include <soc/smi.h> #include <soc/amd_pci_int_defs.h> #include <delay.h>