Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47788 )
Change subject: soc/intel/jasperlake: [TEST-ONLY] SPI read CAR test ......................................................................
soc/intel/jasperlake: [TEST-ONLY] SPI read CAR test
Change-Id: I4813572a31240b2796cacfa97044f9ed091ec108 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/jasperlake/bootblock/bootblock.c 1 file changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47788/1
diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c index 96e6268..a1254cf 100644 --- a/src/soc/intel/jasperlake/bootblock/bootblock.c +++ b/src/soc/intel/jasperlake/bootblock/bootblock.c @@ -1,10 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h> +#include <console/console.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> #include <intelblocks/uart.h> #include <soc/bootblock.h> +#include <string.h> +
asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { @@ -22,6 +25,31 @@ uart_bootblock_init(); }
+static void report_cache_info(void) +{ + struct cpuid_result res; + uintptr_t addr = 0xFF000000; + char buf[1024]; + uint32_t kbcount=0; + res = cpuid_ext(0x04, 0x03); + const size_t assoc = CPUID_CACHE_WAYS_OF_ASSOC(res) + 1; + const size_t partitions = CPUID_CACHE_PHYS_LINE(res) + 1; + const size_t cache_line_size = CPUID_CACHE_COHER_LINE(res) + 1; + const size_t number_of_sets = CPUID_CACHE_NO_OF_SETS(res) + 1; + const size_t cache_size = assoc * partitions * cache_line_size * number_of_sets; + printk(BIOS_INFO, "assoc=%zd par=%zd line_size=%zd sets=%zd\n", + assoc, partitions, cache_line_size, number_of_sets); + printk(BIOS_INFO, "@@ dedede cache_size 0x%lx bytes\n", cache_size); + + while (addr < 0xFFFF0000) { + memcpy(buf, (void *)addr, 1024); + printk(BIOS_ERR, "TEST : %lx %x KBcount : %d \n", addr, buf[0], kbcount); + addr += 1024; + ++kbcount; + } + +} + void bootblock_soc_init(void) { report_platform_info(); @@ -29,4 +57,5 @@
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ tco_configure(); + report_cache_info(); }