[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8195: fix GPIO register offset

[Hung-Te Lin (Code Review)]

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55163 )

Change subject: soc/mediatek/mt8195: fix GPIO register offset
......................................................................

Patch Set 4:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/55163/comment/f99babbe_673a30cb 
PS1, Line 9: Fix GPIO pu/pd offset.
> In file MT8195 Register Map_V0.2 -1.pdf […]

Thanks. Please put this in commit description

soc/mediatek/mt8195: fix GPIO register offset

Correct the offsets by MT8195 Register Map V0.2-1
 chapter: 3.2 GPIO Controller (page 3272)

Control register names:
    PUPD_CFG0
    PU_CFG0