[coreboot-gerrit] Change in coreboot[master]: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register

[HAOUAS Elyes (Code Review)]

Hello build bot (Jenkins), David Guckian, Vanessa Eusebio, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40842

to look at the new patch set (#2).

Change subject: soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register
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soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register

Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b
Signed-off-by: Elyes HAOUAS 
---
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/smihandler.c
2 files changed, 9 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/40842/2