[coreboot-gerrit] Change in ...coreboot[master]: mb/asrock/h110m: set serirq_mode to continuous mode

[Nico Huber (Code Review)]

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33801 )

Change subject: mb/asrock/h110m: set serirq_mode to continuous mode
......................................................................

mb/asrock/h110m: set serirq_mode to continuous mode

By default, the LPC SIRQ mode is set to Quiet mode. Therefore, COM-port
from the SurerIO chip don't work correctly after the LPC controller (PCI
0:1f.0) initialization. Console output is broken. The patch fixes this
bug by overriding the serirq_mode option in the devicetree.cb to set
Continuous SIRQ mode

Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33801
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/asrock/h110m/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 158801f..3067ffe 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -62,6 +62,9 @@
    register "pirqg_routing" = "PCH_IRQ11"
    register "pirqh_routing" = "PCH_IRQ11"

+	# Set LPC Serial IRQ mode
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
    # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
    # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
    register "PmConfigSlpS3MinAssert" = "0x02"