Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29058
Change subject: amdfam10: Convert to `board_reset()` ......................................................................
amdfam10: Convert to `board_reset()`
And here comes the mess...
This just renames do_hard_reset() to do_board_reset() and keeps current behaviour. As these are never called from chipset or board code but only from common code, it's likely that their implementations are untested and not what we actually want. Also note, that sometimes implementations for rom- and ramstage differ considerably.
Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/asus/kcma-d8/Kconfig M src/mainboard/asus/kfsn4-dre/Kconfig M src/mainboard/asus/kgpe-d16/Kconfig M src/southbridge/amd/amd8111/Kconfig M src/southbridge/amd/amd8111/early_ctrl.c M src/southbridge/amd/amd8111/reset.c M src/southbridge/amd/sb700/Kconfig M src/southbridge/amd/sb700/reset.c M src/southbridge/amd/sb800/Kconfig M src/southbridge/amd/sb800/early_setup.c M src/southbridge/amd/sb800/reset.c M src/southbridge/broadcom/bcm5785/Kconfig M src/southbridge/broadcom/bcm5785/early_setup.c M src/southbridge/broadcom/bcm5785/reset.c M src/southbridge/nvidia/ck804/Kconfig M src/southbridge/nvidia/ck804/early_setup.c M src/southbridge/nvidia/ck804/early_setup_car.c M src/southbridge/nvidia/ck804/reset.c M src/southbridge/nvidia/mcp55/Kconfig M src/southbridge/nvidia/mcp55/early_ctrl.c M src/southbridge/nvidia/mcp55/reset.c 21 files changed, 12 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29058/1
diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index 2d341db..f20cf21 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -17,7 +17,6 @@ select HAVE_ROMSTAGE_CONSOLE_SPINLOCK select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 3e9f3f3..55bd5c3 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -9,7 +9,6 @@ select SOUTHBRIDGE_NVIDIA_CK804 select SUPERIO_WINBOND_W83627THG select PARALLEL_CPU_INIT - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 531ba4f..8028849 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -17,7 +17,6 @@ select HAVE_ROMSTAGE_CONSOLE_SPINLOCK select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK select HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index 5541c93..1436d8c 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -16,7 +16,6 @@ config SOUTHBRIDGE_AMD_AMD8111 bool select IOAPIC - select HAVE_HARD_RESET
config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index f3ba8b6..aa323e4 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -52,7 +52,7 @@ enable_cf9_x(sbbusn, sbdn); }
-void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); /* reset */ diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index fea8891..41d9880 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -37,7 +37,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void do_hard_reset(void) +void do_board_reset(void) { pci_devfn_t dev; unsigned bus; diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 353c2a4..6d62e67 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -22,7 +22,6 @@ def_bool y select IOAPIC select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET select SMBUS_HAS_AUX_CHANNELS
config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index 0878039..f5f7a2c 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -44,7 +44,7 @@ } }
-void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset();
diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index f20fa82..d66469a 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -17,7 +17,6 @@ bool select IOAPIC select HAVE_USBDEBUG_OPTIONS - select HAVE_HARD_RESET
if SOUTHBRIDGE_AMD_SB800
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index badc4a7..d73b75d 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -218,7 +218,7 @@ pmio_write(0x81, byte); }
-void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset();
diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c index e3f36f3..bd578b6 100644 --- a/src/southbridge/amd/sb800/reset.c +++ b/src/southbridge/amd/sb800/reset.c @@ -21,7 +21,7 @@
#include <northbridge/amd/amdk8/reset_test.c>
-void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ diff --git a/src/southbridge/broadcom/bcm5785/Kconfig b/src/southbridge/broadcom/bcm5785/Kconfig index d72afd8..1ec4f8f 100644 --- a/src/southbridge/broadcom/bcm5785/Kconfig +++ b/src/southbridge/broadcom/bcm5785/Kconfig @@ -1,6 +1,5 @@ config SOUTHBRIDGE_BROADCOM_BCM5785 bool - select HAVE_HARD_RESET
config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 766aa1a..c2aa9bc 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -103,7 +103,7 @@ }
-void do_hard_reset(void) +void do_board_reset(void) { bcm5785_enable_wdt_port_cf9();
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 1041aae..ad3ea8f 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -21,7 +21,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */ diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index dbd24b7..338357e 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -1,6 +1,5 @@ config SOUTHBRIDGE_NVIDIA_CK804 bool - select HAVE_HARD_RESET select HAVE_USBDEBUG select IOAPIC
diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index 673c44d..30b68ec 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -310,7 +310,7 @@ return set_ht_link_ck804(4); }
-void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset();
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index 99e6ba7..fbc2719 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -355,7 +355,7 @@ return set_ht_link_ck804(4); }
-void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset();
diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index bcb6dfc..f828c53 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -21,7 +21,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9. */ diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 89aa452..bb1b7df 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -2,7 +2,6 @@ bool select HAVE_USBDEBUG select IOAPIC - select HAVE_HARD_RESET
if SOUTHBRIDGE_NVIDIA_MCP55
diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index e91abdf..66ceae2 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -29,7 +29,7 @@ outb(0x06, 0x0cf9); }
-void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset();
diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 7be98d7..d6f7f6f 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -24,7 +24,7 @@
#include "../../../northbridge/amd/amdk8/reset_test.c"
-void do_hard_reset(void) +void do_board_reset(void) { set_bios_reset(); /* Try rebooting through port 0xcf9 */