Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47173 )
Change subject: soc/intel/xeon_sp: Don't add MC resource twice ......................................................................
Patch Set 1:
(1 comment)
In this case the values are actually coming from FSP, and not directly read from hardware. They are somewhat arbitrarily tied to the MC device (of which there is one per CPU) because it makes sense to have memory sizing be owned by the memory controller. But in this instance there is no actual hardware touched.
I'm not convinced, see inline comment.
https://review.coreboot.org/c/coreboot/+/47173/1/src/soc/intel/xeon_sp/uncor... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/47173/1/src/soc/intel/xeon_sp/uncor... PS1, Line 66: value |= (uint64_t)pci_read_config32(dev, entry->reg); This looks like a hardware access to me.