Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8104
-gerrit
commit 903ffbbf01bcf4a10ac6db52a2ae0801653da5c5 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Tue Jan 6 02:44:20 2015 +1100
{north,south}bridge/*: Use system include path syntax over relative local
Change-Id: Ib7fe3a9d672a02c9a91e3b320fefdbd98fd16cff Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/northbridge/amd/gx2/northbridge.c | 2 +- src/northbridge/amd/lx/northbridge.c | 2 +- src/northbridge/amd/lx/raminit.c | 2 +- src/northbridge/intel/gm45/gm45.h | 5 ++--- src/northbridge/intel/gm45/gma.c | 2 +- src/northbridge/intel/haswell/report_platform.c | 2 +- src/northbridge/intel/i945/i945.h | 2 +- src/northbridge/intel/nehalem/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit_native.c | 8 ++++---- src/northbridge/intel/sandybridge/report_platform.c | 2 +- src/northbridge/intel/sandybridge/romstage_native.c | 4 ++-- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 2 +- src/southbridge/amd/cs5535/chipsetinit.c | 4 ++-- src/southbridge/dmp/vortex86ex/southbridge.c | 4 ++-- src/southbridge/intel/bd82x6x/early_pch_native.c | 2 +- src/southbridge/intel/bd82x6x/early_rcba.c | 2 +- src/southbridge/intel/bd82x6x/early_thermal.c | 2 +- src/southbridge/intel/bd82x6x/early_usb_native.c | 2 +- src/southbridge/intel/bd82x6x/nvs.h | 3 ++- src/southbridge/intel/bd82x6x/smi.c | 3 +-- src/southbridge/intel/fsp_bd82x6x/nvs.h | 3 ++- src/southbridge/intel/fsp_bd82x6x/smi.c | 2 +- src/southbridge/intel/fsp_rangeley/romstage.c | 8 ++++---- src/southbridge/intel/ibexpeak/early_thermal.c | 2 +- src/southbridge/intel/ibexpeak/nvs.h | 3 ++- src/southbridge/intel/ibexpeak/smi.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- src/southbridge/intel/lynxpoint/nvs.h | 3 ++- 29 files changed, 43 insertions(+), 41 deletions(-)
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index a48226d..aa09e08 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -31,7 +31,7 @@ #include <cpu/x86/cache.h> #include <cpu/amd/vr.h> #include <cpu/cpu.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h>
void print_conf(void);
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4e84025..c4214ad 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -33,7 +33,7 @@ #include <cpu/amd/vr.h> #include <cpu/cpu.h> #include "northbridge.h" -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h>
/* here is programming for the various MSRs.*/ diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 7c95ab4..656c6e5 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -22,7 +22,7 @@ #include <cpu/amd/lxdef.h> #include <arch/io.h> #include <spd.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "raminit.h" #include "northbridge.h"
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 5bdf9e4..4e50aba 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -21,12 +21,11 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__
-#include "southbridge/intel/i82801ix/i82801ix.h" +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <stdint.h>
#ifndef __ACPI__
-#include <stdint.h> - typedef enum { FSB_CLOCK_1067MHz = 0, FSB_CLOCK_800MHz = 1, diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 74e16ad..e366c3f 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -30,7 +30,7 @@ #include <cpu/x86/mtrr.h> #include <kconfig.h>
-#include "drivers/intel/gma/i915_reg.h" +#include <drivers/intel/gma/i915_reg.h> #include "chip.h" #include "gm45.h" #include <drivers/intel/gma/intel_bios.h> diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 8bb4a05..33da3b5 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <arch/cpu.h> #include <string.h> -#include "southbridge/intel/lynxpoint/pch.h" +#include <southbridge/intel/lynxpoint/pch.h> #include <arch/io.h> #include <cpu/x86/msr.h> #include "haswell.h" diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index fe59ebe..651b75a 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -27,7 +27,7 @@ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-#include "../../../southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/i82801gx.h>
/* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 9ca98d5..7d37cb8 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -55,7 +55,7 @@ typedef u32 device_t;
#include "nehalem.h"
-#include "southbridge/intel/ibexpeak/me.h" +#include <southbridge/intel/ibexpeak/me.h>
#if REAL #include <delay.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index f6c92db..0f13f01 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -34,7 +34,7 @@ #include "sandybridge.h"
/* Management Engine is in the southbridge */ -#include "southbridge/intel/bd82x6x/me.h" +#include <southbridge/intel/bd82x6x/me.h>
/* * MRC scrambler seed offsets should be reserved in diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index de6dac7..77c4005 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -36,11 +36,11 @@ #include <lib.h>
/* Management Engine is in the southbridge */ -#include "southbridge/intel/bd82x6x/me.h" +#include <southbridge/intel/bd82x6x/me.h> /* For SPD. */ -#include "southbridge/intel/bd82x6x/smbus.h" -#include "arch/cpu.h" -#include "cpu/x86/msr.h" +#include <southbridge/intel/bd82x6x/smbus.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h>
/* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */ diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 8230729..f189697 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <arch/cpu.h> #include <string.h> -#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/bd82x6x/pch.h> #include <arch/io.h> #include "sandybridge.h"
diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 737cd63..400a079 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -31,8 +31,8 @@ #include <cpu/intel/romstage.h> #include <halt.h> #include "raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h>
void main(unsigned long bist) { diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 59d89b0..1a618b5 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -156,7 +156,7 @@ typedef union _PCI_ADDR { #define cimFusionMsgCMultiCoreDefault FALSE #define cimFusionMsgCStageDefault FALSE
-#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" +#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h>
#if CONFIG_HAVE_ACPI_RESUME #include <spi-generic.h> diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index ab1b640..e6aec1d 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -7,11 +7,11 @@ #include <stdlib.h> #include <string.h> #include "chip.h" -#include "northbridge/amd/gx2/northbridge.h" +#include <northbridge/amd/gx2/northbridge.h> #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> -#include "southbridge/amd/cs5535/cs5535.h" +#include <southbridge/amd/cs5535/cs5535.h>
/* the structs in this file only set msr.lo. But ... that may not always be true */
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 2fe1bc2..c8aeb56 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -26,10 +26,10 @@ #include <pc80/keyboard.h> #include <string.h> #include <delay.h> -#include "arch/io.h" +#include <arch/io.h> #include "chip.h" #include "southbridge.h" -#include "cpu/dmp/dmp_post_code.h" +#include <cpu/dmp/dmp_post_code.h>
/* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */ static const unsigned char irq_to_int_routing[16] = { diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c index 0863f34..a16da96 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_native.c +++ b/src/southbridge/intel/bd82x6x/early_pch_native.c @@ -30,7 +30,7 @@
#include "pch.h" /* For DMI bar. */ -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h>
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 114b174..d63b7b3 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -21,7 +21,7 @@
#include <stdint.h> #include "pch.h" -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h>
void southbridge_configure_default_intmap(void) diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 02ec9a7..2328be3 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -20,7 +20,7 @@
#include <arch/io.h> #include "pch.h" -#include "cpu/intel/model_206ax/model_206ax.h" +#include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/x86/msr.h>
/* Early thermal init, must be done prior to giving ME its memory diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c index b1f8447..f4ce625 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_native.c +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> -#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */ +#include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE. */ #include "pch.h"
void diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 9cdfb13..037d665 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index a20232e..5bb153d 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -19,7 +19,6 @@ * MA 02110-1301 USA */
- #include <device/device.h> #include <device/pci.h> #include <console/console.h> @@ -29,7 +28,7 @@ #include <cpu/x86/smm.h> #include <string.h> #include "pch.h" -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h>
extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_end; diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h index 8557c02..dde07e2 100644 --- a/src/southbridge/intel/fsp_bd82x6x/nvs.h +++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index 827b897..1847b22 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -31,7 +31,7 @@ #include "pch.h"
#if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE -#include "northbridge/intel/fsp_sandybridge/northbridge.h" +#include <northbridge/intel/fsp_sandybridge/northbridge.h> #endif
extern unsigned char _binary_smm_start; diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 6c5751e..d910498 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -30,10 +30,10 @@ #include <cbmem.h> #include <console/console.h> #include <drivers/intel/fsp/fsp_util.h> -#include "northbridge/intel/fsp_rangeley/northbridge.h" -#include "southbridge/intel/fsp_rangeley/soc.h" -#include "southbridge/intel/fsp_rangeley/gpio.h" -#include "southbridge/intel/fsp_rangeley/romstage.h" +#include <northbridge/intel/fsp_rangeley/northbridge.h> +#include <southbridge/intel/fsp_rangeley/soc.h> +#include <southbridge/intel/fsp_rangeley/gpio.h> +#include <southbridge/intel/fsp_rangeley/romstage.h> #include <arch/cpu.h> #include <arch/stages.h> #include <cpu/x86/msr.h> diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index d23749e..fee2269 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -20,7 +20,7 @@
#include <arch/io.h> #include "pch.h" -#include "cpu/intel/model_2065x/model_2065x.h" +#include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/x86/msr.h>
/* Early thermal init, must be done prior to giving ME its memory diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 9cdfb13..037d665 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 2ce9072..d83cd0a 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -31,7 +31,7 @@ #include <string.h> #include "pch.h"
-#include "northbridge/intel/nehalem/nehalem.h" +#include <northbridge/intel/nehalem/nehalem.h>
extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_end; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e2032ad..39fc40c 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -36,7 +36,7 @@ * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include "northbridge/intel/nehalem/nehalem.h" +#include <northbridge/intel/nehalem/nehalem.h> #include <arch/pci_mmio_cfg.h>
/* While we read PMBASE dynamically in case it changed, let's diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 81b2321..790953f 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */