[coreboot-gerrit] Change in coreboot[master]: [WIP] nb/intel/haswell/pcie.c: Add some ASPM steps

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47223 )

Change subject: [WIP] nb/intel/haswell/pcie.c: Add some ASPM steps
......................................................................

[WIP] nb/intel/haswell/pcie.c: Add some ASPM steps

Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/haswell/pcie.c
1 file changed, 13 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47223/1

diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c
index d9e77a7..6eba75e 100644
--- a/src/northbridge/intel/haswell/pcie.c
+++ b/src/northbridge/intel/haswell/pcie.c
@@ -5,6 +5,7 @@
 #include <device/pci.h>
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <assert.h>

static void pcie_disable(struct device *dev)
@@ -13,6 +14,17 @@
    dev->enabled = 0;
 }

+static void pcie_init(struct device *dev)
+{
+	/* Enable support for L0s and L1 */
+	pci_or_config32(dev, 0xac, 3 << 10);
+
+	pci_and_config32(dev, 0x200, ~(3 << 26));
+
+	/* Other fields in the register must not be changed while writing this */
+	pci_or_config16(dev, 0x258, 1 << 2);
+}
+
 #if CONFIG(HAVE_ACPI_TABLES)
 static const char *pcie_acpi_name(const struct device *dev)
 {
@@ -54,7 +66,7 @@
    .scan_bus		= pciexp_scan_bridge,
    .reset_bus		= pci_bus_reset,
    .disable		= pcie_disable,
-	.init			= pci_dev_init,
+	.init			= pcie_init,
    .ops_pci		= &pci_dev_ops_pci,
 #if CONFIG(HAVE_ACPI_TABLES)
    .acpi_name		= pcie_acpi_name,