Anastasios Koutian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83269?usp=email )
Change subject: cpu/intel/model_206ax: Allow PL1/PL2 configuration ......................................................................
cpu/intel/model_206ax: Allow PL1/PL2 configuration
Tested on ThinkPad T420 with the i7-3940XM.
Change-Id: I064af25ec4805fae755eea52c4c9c6d4386c0aee Signed-off-by: Anastasios Koutian akoutian2@gmail.com --- M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/northbridge/intel/sandybridge/northbridge.c 4 files changed, 22 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/83269/1
diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 9080e2f..e20dd1a 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -42,6 +42,10 @@ enum cpu_acpi_level acpi_c3;
int tcc_offset; /* TCC Activation Offset */ + + int pl1; /* Long-term power limit*/ + int pl2; /* Short-term power limit*/ + int pp0_current_limit; /* Primary Plane Current Limit (Icc) in Amps */ int pp1_current_limit; /* Secondary Plane Current Limit (IAXG) in Amps */
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 9a2fefb..2338f29 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -129,7 +129,7 @@ void intel_model_206ax_finalize_smm(void);
/* Configure power limits for turbo mode */ -void set_power_limits(u8 power_limit_1_time); +void set_power_limits(u8 power_limit_1_time, struct device *); int cpu_config_tdp_levels(void);
static inline u8 cpu_stepping(void) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 8a4dd3f..f4eefa3 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -94,8 +94,9 @@ * Configure processor power limits if possible * This must be done AFTER set of BIOS_RESET_CPL */ -void set_power_limits(u8 power_limit_1_time) +void set_power_limits(u8 power_limit_1_time, struct device *dev) { + struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->upstream->children->chip_info; msr_t msr = rdmsr(MSR_PLATFORM_INFO); msr_t limit; unsigned int power_unit; @@ -132,16 +133,26 @@
power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
- /* Set long term power limit to TDP */ limit.lo = 0; - limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + if(conf->pl1) { + printk(BIOS_DEBUG, "%s: setting PL1 to %u microwatts\n", dev_path(dev), conf->pl1); + limit.lo |= ((conf->pl1 * power_unit) / 1000000) & PKG_POWER_LIMIT_MASK; + } else { + /* Set long term power limit to TDP */ + limit.lo |= tdp & PKG_POWER_LIMIT_MASK; + } limit.lo |= PKG_POWER_LIMIT_EN; limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
- /* Set short term power limit to 1.25 * TDP */ limit.hi = 0; - limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + if(conf->pl2){ + printk(BIOS_DEBUG, "%s: setting PL2 to %u microwatts\n", dev_path(dev), conf->pl2); + limit.hi |= ((conf->pl2 * power_unit) / 1000000) & PKG_POWER_LIMIT_MASK; + } else { + /* Set short term power limit to 1.25 * TDP */ + limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK; + } limit.hi |= PKG_POWER_LIMIT_EN; /* Power limit 2 time is only programmable on SNB EP/EX */
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 3db9086..efafac9 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -351,7 +351,7 @@
/* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); - set_power_limits(28); + set_power_limits(28, dev);
/* * CPUs with configurable TDP also need power limits set in MCHBAR.