[coreboot-gerrit] Change in coreboot[master]: mb/purism/librem_mini: Set unused GPIO pads to PAD_NC

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47191 )

Change subject: mb/purism/librem_mini: Set unused GPIO pads to PAD_NC
......................................................................

mb/purism/librem_mini: Set unused GPIO pads to PAD_NC

Set pads A7, A16, B0, B1, B15, D8, D13, F3, H6-H9, H14, H16, H17
to PAD_NC as per board schematics.

Change-Id: I4c2ab936256d0031d7a127fbeac42c8951a0b39f
Signed-off-by: Matt DeVillier 
---
M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
1 file changed, 15 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/47191/1

diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
index 04c8614..9311ca0 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c
@@ -37,7 +37,7 @@

/* GPP_A7 - GPIO */
    /* DW0: 0x44000200, DW1: 0x00000000 */
-	PAD_CFG_GPO(GPP_A7, 0, DEEP),
+	PAD_NC(GPP_A7, NONE),

/* GPP_A8 - CLKRUN# */
    /* DW0: 0x44000700, DW1: 0x00000000 */
@@ -73,7 +73,7 @@

/* GPP_A16 - GPIO */
    /* DW0: 0x84000200, DW1: 0x00003000 */
-	PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, PLTRST),
+	PAD_NC(GPP_A16, UP_20K),

/* GPP_A17 - GPIO */
    /* DW0: 0x84000201, DW1: 0x00000000 */
@@ -107,11 +107,11 @@

/* GPP_B0 - Reserved */
    /* DW0: 0x44000700, DW1: 0x00000000 */
-	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	PAD_NC(GPP_B0, NONE),

/* GPP_B1 - Reserved */
    /* DW0: 0x44000700, DW1: 0x00000000 */
-	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	PAD_NC(GPP_B1, NONE),

/* GPP_B2 - GPIO */
    /* DW0: 0x84000201, DW1: 0x00000000 */
@@ -167,7 +167,7 @@

/* GPP_B15 - GSPI0_CS0# */
    /* DW0: 0x00000701, DW1: 0x00000000 */
-	PAD_CFG_NF(GPP_B15, NONE, PWROK, NF1),
+	PAD_NC(GPP_B15, NONE),

/* GPP_B16 - GSPI0_CLK */
    /* DW0: 0x84000601, DW1: 0x00000000 */
@@ -271,7 +271,7 @@

/* GPP_D8 - GPIO */
    /* DW0: 0x84000200, DW1: 0x00000000 */
-	PAD_CFG_GPO(GPP_D8, 0, PLTRST),
+	PAD_NC(GPP_D8, NONE),

/* GPP_D9 - GPIO */
    /* DW0: 0x84000201, DW1: 0x00000000 */
@@ -291,7 +291,7 @@

/* GPP_D13 - GPIO */
    /* DW0: 0x04000201, DW1: 0x00000000 */
-	PAD_CFG_GPO(GPP_D13, 1, RSMRST),
+	PAD_NC(GPP_D13, NONE),

/* GPP_D14 - GPIO */
    /* DW0: 0x84000201, DW1: 0x00000000 */
@@ -349,7 +349,7 @@

/* GPP_F3 - GPIO */
    /* DW0: 0x84000200, DW1: 0x00003000 */
-	PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST),
+	PAD_NC(GPP_F3, UP_20K),

/* GPP_F4 - CNV_BRI_DT */
    /* DW0: 0x44000700, DW1: 0x00003000 */
@@ -459,19 +459,19 @@

/* GPP_H6 - I2C3_SDA */
    /* DW0: 0x44000702, DW1: 0x00000000 */
-	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	PAD_NC(GPP_H6, NONE),

/* GPP_H7 - I2C3_SCL */
    /* DW0: 0x44000702, DW1: 0x00000000 */
-	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	PAD_NC(GPP_H7, NONE),

/* GPP_H8 - I2C4_SDA */
    /* DW0: 0x44000702, DW1: 0x00000000 */
-	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+	PAD_NC(GPP_H8, NONE),

/* GPP_H9 - I2C4_SCL */
    /* DW0: 0x44000702, DW1: 0x00000000 */
-	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+	PAD_NC(GPP_H9, NONE),

/* GPP_H10 - I2C5_SDA */
    /* DW0: 0x84000603, DW1: 0x00000000 */
@@ -491,7 +491,7 @@

/* GPP_H14 - GPIO */
    /* DW0: 0x84000200, DW1: 0x00000000 */
-	PAD_CFG_GPO(GPP_H14, 0, PLTRST),
+	PAD_NC(GPP_H14, NONE),

/* GPP_H15 - GPIO */
    /* DW0: 0x84000201, DW1: 0x00000000 */
@@ -499,11 +499,11 @@

/* GPP_H16 - GPIO */
    /* DW0: 0x04000201, DW1: 0x00000000 */
-	PAD_CFG_GPO(GPP_H16, 1, RSMRST),
+	PAD_NC(GPP_H16, NONE),

/* GPP_H17 - GPIO */
    /* DW0: 0x04000201, DW1: 0x00000000 */
-	PAD_CFG_GPO(GPP_H17, 1, RSMRST),
+	PAD_NC(GPP_H17, NONE),

/* GPP_H18 - CPU_C10_GATE# */
    /* DW0: 0x44000700, DW1: 0x00000000 */