[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/alderlake: Add a few missing definitions in iomap.h

[Nick Vaccaro (Code Review)]

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72635 )

Change subject: soc/intel/alderlake: Add a few missing definitions in iomap.h
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soc/intel/alderlake: Add a few missing definitions in iomap.h

Some reserved address range listed in Alder Lake Platform Firmware
Architecture Specification document 626540 section 6.4 ADL - System
Memory Map such as North TraceHub ranges were missing. Details about
North TraceHub (aka. Intel TraceHub) can be found in Intel Trace
Hub (Intel TH) Developer's Manual document 671536.

BUG=b:264648959
TEST=Compilation successful

Change-Id: I14803a7297c8c5edefe564d92bfe7314f6769942
Signed-off-by: Jeremy Compostella 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72635
Tested-by: build bot (Jenkins) 
Reviewed-by: YH Lin 
Reviewed-by: Eric Lai 
Reviewed-by: Nick Vaccaro 
---
M src/soc/intel/alderlake/include/soc/iomap.h
1 file changed, 40 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  YH Lin: Looks good to me, approved
  Nick Vaccaro: Looks good to me, approved
  Eric Lai: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h
index 0c332be..6dd3bec 100644
--- a/src/soc/intel/alderlake/include/soc/iomap.h
+++ b/src/soc/intel/alderlake/include/soc/iomap.h
@@ -23,6 +23,22 @@
 #define PCH_PRESERVED_BASE_ADDRESS	0xfc800000
 #define PCH_PRESERVED_BASE_SIZE		0x02000000

+/* North (Intel) TraceHub Software. */
+#define NTH_SW_BASE_ADDRESS	0xfc000000
+#define NTH_SW_BASE_SIZE	0x800000
+
+/* North (Intel) TraceHub Firmware. */
+#define NTH_FW_BASE_ADDRESS	0xfae00000
+#define NTH_FW_BASE_SIZE	0x200000
+
+/* North (Intel) TraceHub Memory storage controller Trace Buffer. */
+#define NTH_MTB_BASE_ADDRESS	0xfad00000
+#define NTH_MTB_BASE_SIZE	0x100000
+
+/* North (Intel) TraceHub Real Time Instruction Trace. */
+#define NTH_RTIT_BASE_ADDRESS	0xfacfc000
+#define NTH_RTIT_BASE_SIZE	0x4000
+
 #define UART_BASE_SIZE		0x1000

#define UART_BASE_0_ADDRESS	0xfe03e000