Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42436 )
Change subject: mb/google/volteer: Override power limits with SKU-specific limits ......................................................................
mb/google/volteer: Override power limits with SKU-specific limits
Using guidance from Intel, a new set of power limits (PL1, PL2 & PL4) are available for TGL-U. They are dependent upon the SKU of the CPU that the mainboard is running on. Volteer is updated here to use these new limits.
To accomplish this, the SoC chip config's power_limits_config member was expanded to an array, which can be indexed by POWER_LIMITS_*_CORE macros. Just before power limits are applied, the correct set of them is chosen from the array based on System Agent PCI ID. Therefore, a TGL board should have two sets of power limits available in the devicetree.
BUG=b:152639350 TEST=On a Volteer SKU4 (4-core), verified the following console output: CPU PL1 = 15 Watts CPU PL2 = 60 Watts CPU PL4 = 105 Watts
Change-Id: I18a66fc3aacbb3ab594b2e3d6e2a4ad84c10d8f0 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/42436 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Caveh Jalali caveh@chromium.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/systemagent.c 3 files changed, 40 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, but someone else must approve Caveh Jalali: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 8cd926c..f2e427f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -198,9 +198,15 @@ # Enable DPTF register "dptf_enable" = "1"
- register "power_limits_config" = "{ + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 60, + .tdp_pl4 = 105, + }" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 38, + .tdp_pl4 = 71, }"
register "Device4Enable" = "1" diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 30377aa..8b1fe2d 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -22,6 +22,11 @@ #define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SSP_LINKS 6
+/* The first two are for TGL-U */ +#define POWER_LIMITS_U_4_CORE 0 +#define POWER_LIMITS_U_2_CORE 1 +#define POWER_LIMITS_MAX 2 + /* * Enable External V1P05 Rail in: BIT0:S0i1/S0i2, * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 @@ -55,7 +60,7 @@ struct soc_intel_common_config common_soc_config;
/* Common struct containing power limits configuration information */ - struct soc_power_limits_config power_limits_config; + struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX];
/* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 08d1ef3..e428365 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -6,9 +6,11 @@ * Chapter number: 3 */
+#include <console/console.h> #include <device/device.h> #include <delay.h> #include <device/pci.h> +#include <device/pci_ids.h> #include <device/pci_ops.h> #include <intelblocks/power_limit.h> #include <intelblocks/systemagent.h> @@ -53,8 +55,14 @@ void soc_systemagent_init(struct device *dev) { struct soc_power_limits_config *soc_config; + struct device *sa; + uint16_t sa_pci_id; config_t *config;
+ /* Get System Agent PCI ID */ + sa = pcidev_path_on_root(SA_DEVFN_ROOT); + sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr();
@@ -64,7 +72,25 @@ /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); config = config_of_soc(); - soc_config = &config->power_limits_config; + + /* + * Choose a power limits configuration based on the SoC SKU, + * differentiated here based on SA PCI ID. + */ + switch (sa_pci_id) { + case PCI_DEVICE_ID_INTEL_TGL_ID_U: + case PCI_DEVICE_ID_INTEL_TGL_ID_U_1: + soc_config = &config->power_limits_config[POWER_LIMITS_U_4_CORE]; + break; + case PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2: + soc_config = &config->power_limits_config[POWER_LIMITS_U_2_CORE]; + break; + default: + printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits " + "configuration\n", sa_pci_id); + return; + } + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); }