[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add config for sata devslp pad reset configuration

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
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soc/intel/cannonlake: Add config for sata devslp pad reset configuration

CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.

Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.h
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35306/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2ebe017..8b74aec 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -139,6 +139,7 @@
    uint8_t SataSalpSupport;
    uint8_t SataPortsEnable[8];
    uint8_t SataPortsDevSlp[8];
+	uint8_t SataPortsDevSlpResetConfig[8];

/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
    uint8_t SlpS0WithGbeSupport;