Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Rizwan Qureshi, V Sowmya, build bot (Jenkins), Andrey Petrov, Patrick Georgi, Martin Roth, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35403
to look at the new patch set (#27).
Change subject: soc/intel/common/basecode: Implement CSE update flow ......................................................................
soc/intel/common/basecode: Implement CSE update flow
This is the core patch that implement CSE FW update flow.
To enable the FW update flow the following are required:
* Descriptor change to accommodate a larger CSME region The CSME size is 6MB for the POC.
* FMAP changes to accommodate ME update binary in RW CBFSes. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified.
* The new CSE binary with new partitions and respective RW area binaries.
The following changes have been done in this patch:
* Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. Send global reset command to reset only the CSME Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command Erase and Copy the CBFS ME RW to ME RW partition Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command Trigger global reset The system should boot with the Updated ME
Verified that the basic update flows are working on Cometlake RVP and hatch.
Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com Signed-off-by: V Sowmya v.sowmya@intel.com Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com --- A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 4 files changed, 446 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/27