[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801ix: Use common AHCI

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37141 )

Change subject: sb/intel/i82801ix: Use common AHCI
......................................................................

sb/intel/i82801ix: Use common AHCI

Untested.

Change-Id: I4ef0d152ef17a237c0604a3d1f78fcd97a016cf7
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/i82801ix/Kconfig
M src/southbridge/intel/i82801ix/sata.c
2 files changed, 12 insertions(+), 50 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37141/1

diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 8363978..9ef680b 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -16,6 +16,7 @@

config SOUTHBRIDGE_INTEL_I82801IX
    bool
+	select SOUTHBRIDGE_INTEL_COMMON_AHCI
    select SOUTHBRIDGE_INTEL_COMMON_SMBUS
    select SOUTHBRIDGE_INTEL_COMMON_SPI if !BOARD_EMULATION_QEMU_X86_Q35
    select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index fa6c1df..7143fa2 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -24,60 +24,13 @@
 #include <device/pci_ids.h>
 #include <pc80/mc146818rtc.h>
 #include <types.h>
+#include <southbridge/intel/common/ahci.h>

#include "chip.h"
 #include "i82801ix.h"

typedef struct southbridge_intel_i82801ix_config config_t;

-static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map,
-				  const int is_mobile)
-{
-	int i;
-	u32 reg32;
-	struct resource *res;
-
-	/* Initialize AHCI memory-mapped space */
-	res = find_resource(dev, PCI_BASE_ADDRESS_5);
-	if (!res)
-		return;
-
-	u8 *abar = res2mmio(res, 0, 0);
-	printk(BIOS_DEBUG, "ABAR: %p\n", abar);
-
-	/* Set AHCI access mode.
-	   No other ABAR registers should be accessed before this. */
-	reg32 = read32(abar + 0x04);
-	reg32 |= 1 << 31;
-	write32(abar + 0x04, reg32);
-
-	/* CAP (HBA Capabilities) : enable power management */
-	reg32 = read32(abar + 0x00);
-	/* CCCS must be set. */
-	reg32 |= 0x0c006080;  /* set CCCS+PSC+SSC+SALP+SSS */
-	reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */
-	write32(abar + 0x00, reg32);
-
-	/* PI (Ports implemented) */
-	write32(abar + 0x0c, port_map);
-	/* PCH code reads back twice, do we need it, too? */
-	(void) read32(abar + 0x0c); /* Read back 1 */
-	(void) read32(abar + 0x0c); /* Read back 2 */
-
-	/* VSP (Vendor Specific Register) */
-	reg32 = read32(abar + 0xa0);
-	reg32 &= ~0x00000001; /* clear SLPD */
-	write32(abar + 0xa0, reg32);
-
-	/* Lock R/WO bits in Port command registers. */
-	for (i = 0; i < 6; ++i) {
-		if (((i == 2) || (i == 3)) && is_mobile)
-			continue;
-		u8 *addr = abar + 0x118 + (i * 0x80);
-		write32(addr, read32(addr));
-	}
-}
-
 static void sata_program_indexed(struct device *const dev, const int is_mobile)
 {
    u32 reg32;
@@ -228,8 +181,16 @@
    	}
    }

-	if (sata_mode == 0)
-		sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile);
+	if (sata_mode == 0) {
+		u32 port_map;
+
+		port_map = config->sata_port_map;
+		if (is_mobile)
+			port_map &= ~(3 << 2);
+
+		/* Initialize AHCI memory-mapped space */
+		sb_ahci_init(dev, port_map, false, true, 0, false, 1);
+	}

sata_program_indexed(dev, is_mobile);
 }