[coreboot-gerrit] Change in ...coreboot[master]: drivers/intel/fsp1_1: Adjust postcar MTRRs

[Kyösti Mälkki (Code Review)]

Hello Aaron Durbin, Arthur Heymans, Frans Hendriks, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33927

to look at the new patch set (#2).

Change subject: drivers/intel/fsp1_1: Adjust postcar MTRRs
......................................................................

drivers/intel/fsp1_1: Adjust postcar MTRRs

Use of romstage_ram_stack_bottom() was invalid, it
potentially uses a different ROMSTAGE_RAM_STACK_SIZE
from the postcar_frame_init() call.

If alignment evaluated to 1 MiB, that WB MTRR may not
have covered all of CBMEM range, having some impact
on boot speeds.

There is no need to accurately describe write-back
MTRR ranges for postcar.

Change-Id: Icb65cef079df56fadcc292c648cab8bdbb667f47
Signed-off-by: Kyösti Mälkki 
---
M src/drivers/intel/fsp1_1/car.c
1 file changed, 7 insertions(+), 49 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/33927/2