[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans.

Hello Arthur Heymans,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/81280?usp=email

to review the following change.

Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support
......................................................................

soc/intel/xeon_sp/spr: Enable x86_64 support

Fix compilation errors when compiled for x86_64.

Test: Booted on ibm/sbp1 to linux payload.

Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/spr/Kconfig
M src/soc/intel/xeon_sp/spr/romstage.c
M src/soc/intel/xeon_sp/spr/upd_display.c
M src/soc/intel/xeon_sp/uncore_acpi.c
4 files changed, 14 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/81280/1

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 6b8a106..646c66a 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -17,6 +17,7 @@
    select UDK_202005_BINDING
    select SOC_INTEL_HAS_CXL
    select USE_COREBOOT_COMPLEMENTARY_FSP_HEADERS
+	select HAVE_EXP_X86_64_SUPPORT
    help
      Intel Sapphire Rapids-SP support

diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index af86f71..e1284ac 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -119,7 +119,7 @@
 {
    unsigned int port, socket;

-	mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32)spr_iio_bifur_table;
+	mupd->FspmConfig.IioPcieConfigTablePtr = (uintptr_t)spr_iio_bifur_table;
    /* MAX_SOCKET is the maximal number defined by FSP, currently is 4. */
    mupd->FspmConfig.IioPcieConfigTableNumber = MAX_SOCKET;
    UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
@@ -135,7 +135,7 @@
    	PciePortConfig[socket].PcieMaxReadRequestSize = 0x5;
    }

-	mupd->FspmConfig.DeEmphasisPtr = (UINT32)deemphasis_list;
+	mupd->FspmConfig.DeEmphasisPtr = (uintptr_t)deemphasis_list;
    mupd->FspmConfig.DeEmphasisNumber = MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET;
    UINT8 *DeEmphasisConfig = (UINT8 *)deemphasis_list;

@@ -280,7 +280,7 @@
    	UPD_IIO_PCIE_PORT_CONFIG *iio_pcie_cfg;
    	int socket;

-		iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
+		iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr;

for (socket = 0; socket < MAX_SOCKET; socket++)
    		iio_pcie_cfg[socket].PcieGlobalAspm = 0;
diff --git a/src/soc/intel/xeon_sp/spr/upd_display.c b/src/soc/intel/xeon_sp/spr/upd_display.c
index c69a9a0..b3c0c7c 100644
--- a/src/soc/intel/xeon_sp/spr/upd_display.c
+++ b/src/soc/intel/xeon_sp/spr/upd_display.c
@@ -12,7 +12,7 @@
    int port, socket;

UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
-		(UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
+		(UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr;

printk(BIOS_SPEW, "UPD values for IIO:\n");
    for (socket = 0; socket < mupd->FspmConfig.IioPcieConfigTableNumber; socket++) {
@@ -94,7 +94,7 @@
    	       PciePortConfig[socket].PcieMaxReadRequestSize);
    }

-	UINT8 *DeEmphasisConfig = (UINT8 *)mupd->FspmConfig.DeEmphasisPtr;
+	UINT8 *DeEmphasisConfig = (UINT8 *)(uintptr_t)mupd->FspmConfig.DeEmphasisPtr;
    for (port = 0; port < mupd->FspmConfig.DeEmphasisNumber; port++) {
    	printk(BIOS_SPEW, "port: %d, DeEmphasisConfig: 0x%x\n", port,
    	       DeEmphasisConfig[port]);
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index 12d99da..b441f0e 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -20,6 +20,9 @@
 #include <soc/soc_util.h>
 #include <soc/util.h>
 #include <intelblocks/p2sb.h>
+#include <stddef.h>
+#include <stdint.h>
+
 #include "chip.h"

/* NUMA related ACPI table generation. SRAT, SLIT, etc */
@@ -452,11 +455,11 @@
    }

unsigned long tmp = current;
-	printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, "
-		"End Address (limit): 0x%x\n",
-		0, (uint32_t)ptr, (uint32_t)((uint32_t)ptr + size - 1));
-	current += acpi_create_dmar_rmrr(current, 0, (uint32_t)ptr,
-		(uint32_t)((uint32_t)ptr + size - 1));
+	printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%lx, "
+		"End Address (limit): 0x%lx\n",
+	       0, (uintptr_t) ptr,  (size_t)((uintptr_t)ptr + size - 1));
+	current += acpi_create_dmar_rmrr(current, 0, (uintptr_t) ptr,
+					 (size_t) ((uintptr_t)ptr + size - 1));

printk(BIOS_DEBUG, "    [PCI Endpoint Device] PCI Bus Number: 0x%x, "
    	"PCI Path: 0x%x, 0x%x\n",