[coreboot-gerrit] [S] Change in coreboot[master]: nb/intel/x4x: Use read32p()

[Elyes Haouas (Code Review)]

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70287 )

Change subject: nb/intel/x4x: Use read32p()
......................................................................

nb/intel/x4x: Use read32p()

Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082
Signed-off-by: Elyes Haouas 
---
M src/northbridge/intel/x4x/bootblock.c
1 file changed, 11 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/70287/1

diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index 80375a7..71a0609 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -21,7 +21,7 @@
 void bootblock_early_northbridge_init(void)
 {
    /* Disable LaGrande Technology (LT) */
-	read32((void *)TPM_BASE_ADDRESS);
+	read32p(TPM_BASE_ADDRESS);

const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
    pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);