Philipp Hug has posted comments on this change. ( https://review.coreboot.org/27397 )
Change subject: riscv: add trampoline in MBR block to support boot mode 1 ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/27397/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/27397/3//COMMIT_MSG@11 PS3, Line 11: issues.
Stack alignment? How is that influenced? […]
The trampoline part contains the location of the bootblock, so if the change is split, the jump would need to change as well.
The reason for this is, that the same code can be run directly and also when copied by the ZSBL.
And the linker complains when putting the stack at a non 0x1000-aligned address. /home/user/dev/coreboot/util/crossgcc/xgcc/bin/riscv64-elf-ld.bfd: stack must be aligned to 4096!