[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add macros and SPD information for DDR4

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39866 )

Change subject: soc/intel/tigerlake: Add macros and SPD information for DDR4
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soc/intel/tigerlake: Add macros and SPD information for DDR4

This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.

Memory initialization support for DDR4 will be added in a follow-up
change.

Signed-off-by: Furquan Shaikh 
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
---
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/39866/1

diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
index 82d632e..652cbab 100644
--- a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
+++ b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h
@@ -12,6 +12,7 @@
 #include <stdint.h>
 #include <fsp/soc_binding.h>

+#define DIMMS_PER_CHANNEL	2
 #define BYTES_PER_CHANNEL	2
 #define BITS_PER_BYTE		8
 #define DQ_PER_CHANNEL		(BYTES_PER_CHANNEL * BITS_PER_BYTE)
@@ -20,8 +21,13 @@

#define LPDDR4X_CHANNELS	8

+#define DDR4_CHANNELS		2
+#define DDR4_DIMM_SLOTS	(DIMMS_PER_CHANNEL * DDR4_CHANNELS)
+
 enum mem_topology {
    MEMORY_DOWN, /* Supports reading SPD from CBFS or in-memory pointer. */
+	SODIMM, /* Supports reading SPD using SMBus. */
+	MIXED,  /* Only DDR4 supports this (CH0 = MD, CH1 = SODIMM) */
 };

enum md_spd_loc {
@@ -44,6 +50,9 @@
    	uintptr_t data_ptr;
    	size_t data_len;
    };
+
+	/* SPD info for SODIMM topology */
+	uint8_t smbus_addr[DDR4_DIMM_SLOTS];
 };

/* Board-specific memory configuration information */