Attention is currently required from: Reka Norman, Tim Wawrzynczak. Hello Reka Norman,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/63366
to review the following change.
Change subject: mb/google/brya/var/nereid: Configure Type-C CSE strap based on fw_config ......................................................................
mb/google/brya/var/nereid: Configure Type-C CSE strap based on fw_config
The Type-C Port 2 CSE strap needs to be configured differently for Type-C and HDMI. To allow using a single firmware variant for both cases, update the strap at runtime based on fw_config. This is a temporary workaround while we find a better solution.
BUG=b:226848617 TEST=Type-C and HDMI both work on nereid with fw_config set correctly.
Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e Signed-off-by: Reka Norman rekanorman@google.com --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/bootblock.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/brya/variants/nereid/Makefile.inc M src/mainboard/google/brya/variants/nereid/variant.c 5 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/63366/1
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 3126d28..c4a8530 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -90,6 +90,7 @@
config BOARD_GOOGLE_NEREID bool "-> Nereid" + select ALDERLAKE_CONFIGURE_CSE_DESCRIPTOR select BOARD_GOOGLE_BASEBOARD_NISSA
config BOARD_GOOGLE_PRIMUS diff --git a/src/mainboard/google/brya/bootblock.c b/src/mainboard/google/brya/bootblock.c index 1815615..c24e959 100644 --- a/src/mainboard/google/brya/bootblock.c +++ b/src/mainboard/google/brya/bootblock.c @@ -10,3 +10,10 @@ pads = variant_early_gpio_table(&num); gpio_configure_pads(pads, num); } + +void bootblock_mainboard_init(void) +{ + variant_update_descriptor(); +} + +void __weak variant_update_descriptor(void) {} diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index 9accc08..f890171 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -35,6 +35,8 @@ /* Modify devictree settings during ramstage */ void variant_devtree_update(void);
+void variant_update_descriptor(void); + struct cpu_power_limits { uint16_t mchid; u8 cpu_tdp; diff --git a/src/mainboard/google/brya/variants/nereid/Makefile.inc b/src/mainboard/google/brya/variants/nereid/Makefile.inc index 2e8157e..16c9748 100644 --- a/src/mainboard/google/brya/variants/nereid/Makefile.inc +++ b/src/mainboard/google/brya/variants/nereid/Makefile.inc @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +bootblock-y += variant.c
romstage-y += gpio.c romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/nereid/variant.c b/src/mainboard/google/brya/variants/nereid/variant.c index 967fc9a..11aeb40 100644 --- a/src/mainboard/google/brya/variants/nereid/variant.c +++ b/src/mainboard/google/brya/variants/nereid/variant.c @@ -1,7 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <baseboard/variants.h> +#include <console/console.h> #include <drivers/intel/gma/opregion.h> #include <fw_config.h> +#include <soc/bootblock.h> + +#define CPU_DESC_5_BYTE1 0xc7c +#define CPU_DESC_5_BYTE1_VALUE_TYPEC 0xee +#define CPU_DESC_5_BYTE1_VALUE_HDMI 0x1e
const char *mainboard_vbt_filename(void) { @@ -10,3 +17,14 @@
return "vbt.bin"; } + +void variant_update_descriptor(void) +{ + if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_HDMI))) { + printk(BIOS_DEBUG, "Configuring CSE strap for HDMI\n"); + configure_cse_descriptor(CPU_DESC_5_BYTE1, CPU_DESC_5_BYTE1_VALUE_HDMI); + } else { + printk(BIOS_DEBUG, "Configuring CSE strap for Type-C\n"); + configure_cse_descriptor(CPU_DESC_5_BYTE1, CPU_DESC_5_BYTE1_VALUE_TYPEC); + } +}