[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Drop reg-script for SA lockdown

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46324 )

Change subject: soc/intel/broadwell: Drop reg-script for SA lockdown
......................................................................

soc/intel/broadwell: Drop reg-script for SA lockdown

We can just use proper code instead.

Change-Id: I91cd0aa61ba6bc578c892c1a5bc973bf4c28d019
Signed-off-by: Angel Pons 
---
M src/soc/intel/broadwell/finalize.c
1 file changed, 25 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/46324/1

diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c
index bec62fb..1c5423c 100644
--- a/src/soc/intel/broadwell/finalize.c
+++ b/src/soc/intel/broadwell/finalize.c
@@ -3,6 +3,8 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <console/post_codes.h>
+#include <device/device.h>
+#include <device/pci_ops.h>
 #include <reg_script.h>
 #include <spi-generic.h>
 #include <soc/pci_devs.h>
@@ -13,33 +15,6 @@
 #include <soc/systemagent.h>
 #include <southbridge/intel/common/spi.h>

-const struct reg_script system_agent_finalize_script[] = {
-	REG_PCI_OR16(0x50, 1 << 0),				/* GGC */
-	REG_PCI_OR32(0x5c, 1 << 0),				/* DPR */
-	REG_PCI_OR32(0x78, 1 << 10),				/* ME */
-	REG_PCI_OR32(0x90, 1 << 0),				/* REMAPBASE */
-	REG_PCI_OR32(0x98, 1 << 0),				/* REMAPLIMIT */
-	REG_PCI_OR32(0xa0, 1 << 0),				/* TOM */
-	REG_PCI_OR32(0xa8, 1 << 0),				/* TOUUD */
-	REG_PCI_OR32(0xb0, 1 << 0),				/* BDSM */
-	REG_PCI_OR32(0xb4, 1 << 0),				/* BGSM */
-	REG_PCI_OR32(0xb8, 1 << 0),				/* TSEGMB */
-	REG_PCI_OR32(0xbc, 1 << 0),				/* TOLUD */
-	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0),	/* PAVP */
-	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31),	/* SA PM */
-	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0),	/* UMA GFX */
-	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0),	/* VTDTRK */
-	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31),
-	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31),
-	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0),
-	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f),
-	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
-	REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5),
-	REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f),	/* MC */
-
-	REG_SCRIPT_END
-};
-
 const struct reg_script pch_finalize_script[] = {
 #if !CONFIG(SPI_CONSOLE)
    /* Lock SPIBAR */
@@ -74,7 +49,29 @@

printk(BIOS_DEBUG, "Finalizing chipset.\n");

-	reg_script_run_on_dev(sa_dev, system_agent_finalize_script);
+	pci_or_config16(sa_dev, 0x50, 1 << 0);	/* GGC */
+	pci_or_config32(sa_dev, 0x5c, 1 << 0);	/* DPR */
+	pci_or_config32(sa_dev, 0x78, 1 << 10);	/* ME */
+	pci_or_config32(sa_dev, 0x90, 1 << 0);	/* REMAPBASE */
+	pci_or_config32(sa_dev, 0x98, 1 << 0);	/* REMAPLIMIT */
+	pci_or_config32(sa_dev, 0xa0, 1 << 0);	/* TOM */
+	pci_or_config32(sa_dev, 0xa8, 1 << 0);	/* TOUUD */
+	pci_or_config32(sa_dev, 0xb0, 1 << 0);	/* BDSM */
+	pci_or_config32(sa_dev, 0xb4, 1 << 0);	/* BGSM */
+	pci_or_config32(sa_dev, 0xb8, 1 << 0);	/* TSEGMB */
+	pci_or_config32(sa_dev, 0xbc, 1 << 0);	/* TOLUD */
+
+	MCHBAR32(0x5500) |= (1 <<  0);	/* PAVP */
+	MCHBAR32(0x5f00) |= (1 << 31);	/* SA PM */
+	MCHBAR32(0x6020) |= (1 <<  0);	/* UMA GFX */
+	MCHBAR32(0x63fc) |= (1 <<  0);	/* VTDTRK */
+	MCHBAR32(0x6800) |= (1 << 31);
+	MCHBAR32(0x7000) |= (1 << 31);
+	MCHBAR32(0x7ffc) |= (1 <<  0);
+	MCHBAR32(0x5880) |= (1 <<  5);	/* DDR PTM */
+
+	/* Memory Controller Lockdown */
+	MCHBAR8(0x50fc) = 0x8f;

spi_finalize_ops();
    reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);