[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Enable end of post support

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40612 )

Change subject: soc/intel/jasperlake: Enable end of post support
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soc/intel/jasperlake: Enable end of post support

Send end of post message to CSME.

Change-Id: Ie21dcfc84d331f036090d01ea3e3925b81eea902
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/jasperlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/40612/1

diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 19b9300..f90014c 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -97,6 +97,9 @@
    /* Unlock upper 8 bytes of RTC RAM */
    params->RtcMemoryLock = 0;

+	/* Enable End of Post */
+	params->EndOfPostMessage = 0x01;
+
    /* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
    params->Enable8254ClockGatingOnS3 = 1;