[coreboot-gerrit] Change in coreboot[master]: soc/intel: Add Intel Xeon Scalable Processor support

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )

Change subject: soc/intel: Add Intel Xeon Scalable Processor support
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Patch Set 54:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38548/54/src/soc/intel/xeon_sp/chip... 
File src/soc/intel/xeon_sp/chip.c:

https://review.coreboot.org/c/coreboot/+/38548/54/src/soc/intel/xeon_sp/chip... 
PS54, Line 269: static void assign_bridge_resources(struct iiostack_resource *stack_list,
> Hi Aaron, in Xeon Scalable Processor, there is a concept of (Integrated IO) stack. Each stack can be considered to be a root port, it needs to be assigned with IO/memory resource that is big enough and aligned to meet the needs of all PCIe devices in the stack. This is similar to resource reservation for PCIe bridge device in consideration of PCIe end point devices, but it is one another hierarchy. If any further clarification/discussion is needed, let's chat (through either messenger such as slack or phone call, or both).

Then we should model that more appropriately instead of open coding this approach. Do you think you could write up more concretely the requirements so we can come up with an approach that more accurately fits into coreboot? I feel like we're sidestepping some core coreboot implementation details by taking this approach.