Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78594?usp=email )
Change subject: mb/supermicro/x11: Make use of chipset devicetree ......................................................................
mb/supermicro/x11: Make use of chipset devicetree
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off.
Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb 5 files changed, 54 insertions(+), 92 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index d98c20e..254486c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -28,56 +28,12 @@
device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 01.0 off end # CPU PCIe Port 10 (x16) - device pci 01.1 off end # CPU PCIe Port 11 (x8) - device pci 01.2 off end # CPU PCIe Port 12 (x4) - device pci 02.0 off end # Integrated Graphics Device (IGD) - device pci 04.0 on end # SA thermal subsystem - device pci 05.0 off end # Imaging Unit - device pci 08.0 off end # Gaussion Mixture Model (GMM) - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 off end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 19.0 off end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # I2C #4 - device pci 1b.0 off end # PCH PCIe Port 17 - device pci 1b.1 off end # PCH PCIe Port 18 - device pci 1b.2 off end # PCH PCIe Port 19 - device pci 1b.3 off end # PCH PCIe Port 20 - device pci 1c.0 off end # PCH PCIe Port 1 - device pci 1c.1 off end # PCH PCIe Port 2 - device pci 1c.2 off end # PCH PCIe Port 3 - device pci 1c.3 off end # PCH PCIe Port 4 - device pci 1c.4 off end # PCH PCIe Port 5 - device pci 1c.5 off end # PCH PCIe Port 6 - device pci 1c.6 off end # PCH PCIe Port 7 - device pci 1c.7 off end # PCH PCIe Port 8 - device pci 1d.0 off end # PCH PCIe Port 9 - device pci 1d.1 off end # PCH PCIe Port 10 - device pci 1d.2 off end # PCH PCIe Port 11 - device pci 1d.3 off end # PCH PCIe Port 12 - device pci 1d.4 off end # PCH PCIe Port 13 - device pci 1d.5 off end # PCH PCIe Port 14 - device pci 1d.6 off end # PCH PCIe Port 15 - device pci 1d.7 off end # PCH PCIe Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # SPI #0 - device pci 1e.6 off end # SDXC - device pci 1f.0 on # LPC Interface + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end + device ref heci1 on end + device ref sata on end + device ref lpc_espi on chip superio/common device pnp 2e.0 on end end @@ -85,12 +41,7 @@ device pnp 0c31.0 on end end end - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # SPI Controller - device pci 1f.6 off end # GbE - device pci 1f.7 off end # Intel Trace Hub + device ref smbus on end + device ref fast_spi on end end end diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb index 4d54afe..98bfb04 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb @@ -41,44 +41,47 @@ }"
device domain 0 on - device pci 01.0 on + device ref peg0 on + # Slot JPCIE3 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" - end # CPU PCIE Slot (JPCIE3) - device pci 01.1 on # CPU PCIE Slot (JPCIE2) + end + device ref peg1 on + # Slot JPCIE2 smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth8X" end - device pci 02.0 on end # Integrated Graphics Device (No Output) - device pci 1c.0 on # PCI Express Port 1 + device ref igpu on end + device ref pcie_rp1 on register "PcieRpEnable[0]" = "1" device pci 00.0 on end # GbE end - device pci 1c.1 on # PCI Express Port 2 + device ref pcie_rp2 on register "PcieRpEnable[1]" = "1" device pci 00.0 on end # GbE end - device pci 1c.2 on # PCI Express Port 3 only on -LN4F + device ref pcie_rp3 on register "PcieRpEnable[2]" = "1" device pci 00.0 on end # GbE end - device pci 1c.3 on # PCI Express Port 4 only on -LN4F + device ref pcie_rp4 on register "PcieRpEnable[3]" = "1" device pci 00.0 on end # GbE end - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X" end - device pci 1c.6 on # PCI Express Port 7 + device ref pcie_rp7 on register "PcieRpEnable[6]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end - device pci 1d.0 on # PCI Express Port 9 (Slot JPCIE1) + device ref pcie_rp9 on + # Slot JPCIE1 register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on chip drivers/ipmi # On cold boot it takes a while for the BMC to start the IPMI service register "wait_for_bmc" = "1" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 56b8f9c..b46b220 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -40,30 +40,32 @@ }"
device domain 0 on - device pci 01.0 on end # unused - device pci 01.1 on # PCIE Slot (JPCIE1) + device ref peg0 on end # unused + device ref peg1 on + # Slot JPCIE1 register "PcieRpEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" end - device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1) + device ref pcie_rp1 on + # Slot JPCIE1 register "PcieRpEnable[2]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" end - device pci 1c.2 on # PCI Express Port 3 + device ref pcie_rp3 on device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" device pci 00.0 on end # 10GbE device pci 00.1 on end # 10GbE end - device pci 1d.0 on # PCI Express Port 9 + device ref pcie_rp9 on register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on chip drivers/ipmi use pch_gpio as gpio_dev register "post_complete_gpio" = "GPP_B20" diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 66206a6..29252fe 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -36,25 +36,29 @@
device domain 0 on subsystemid 0x15d9 0x0896 inherit - device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) + device ref peg0 on + # Slot JPCIE6 smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" end - device pci 01.1 on # CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7) + device ref peg1 on + # Slot JPCIE7 smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" end - device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) + device ref pcie_rp1 on + # Slot JPCIE4 register "PcieRpEnable[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpAdvancedErrorReporting[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end - device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) + device ref pcie_rp5 on + # Slot JPCIE5 register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" register "PcieRpAdvancedErrorReporting[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end - device pci 1d.0 on # PCH PCIe Port 9 + device ref pcie_rp9 on register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" register "PcieRpAdvancedErrorReporting[8]" = "1" @@ -62,7 +66,7 @@ subsystemid 0x15d9 0x1533 end end - device pci 1d.1 on # PCH PCIe Port 10 + device ref pcie_rp10 on register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1" register "PcieRpAdvancedErrorReporting[9]" = "1" @@ -70,7 +74,7 @@ subsystemid 0x15d9 0x1533 end end - device pci 1d.2 on # PCH PCIe Port 11 + device ref pcie_rp11 on register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" register "PcieRpAdvancedErrorReporting[10]" = "1" @@ -78,7 +82,7 @@ device pci 00.0 on end # Aspeed 2400 VGA end end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on chip drivers/ipmi use pch_gpio as gpio_dev register "bmc_jumper_gpio" = "GPP_D22" # JPB1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb index c5c2778..29babda 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb @@ -42,32 +42,34 @@ }"
device domain 0 on - device pci 01.0 on + device ref peg0 on + # Slot JSXB1B smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X" - end # CPU PCIE Slot JSXB1B - device pci 1c.0 on # PCI Express Port 1 + end + device ref pcie_rp1 on register "PcieRpEnable[0]" = "1" device pci 00.0 on end # GbE end - device pci 1c.1 on # PCI Express Port 2 + device ref pcie_rp2 on register "PcieRpEnable[1]" = "1" device pci 00.0 on end # GbE end - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end - device pci 1d.0 on # PCI Express Port 9 (Slot JSXB2) + device ref pcie_rp9 on + # Slot JSXB2 register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end - device pci 1d.4 on # PCI Express Port 13 + device ref pcie_rp13 on register "PcieRpEnable[12]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end end - device pci 1f.0 on # LPC Interface + device ref lpc_espi on chip drivers/ipmi # On cold boot it takes a while for the BMC to start the IPMI service register "wait_for_bmc" = "1"