[coreboot-gerrit] Change in coreboot[master]: [WIP]arch/x86: Tear down CAR in ramstage

[Arthur Heymans (Code Review)]

Attention is currently required from: Jason Glenesk, Anjaneya "Reddy" Chagam, Raul Rangel, Marshall Dawson, Jonathan Zhang, Johnny Lin, Morgan Jang, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Felix Held.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54301 )

Change subject: [WIP]arch/x86: Tear down CAR in ramstage
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Patch Set 2:

(1 comment)

File src/cpu/x86/mtrr/earlymtrr.c:

https://review.coreboot.org/c/coreboot/+/54301/comment/31987378_17d4d8ce 
PS2, Line 125: post_car_mtrrs
> Where is this object initialized? It was previously created the by loader of postcar targeting the module parameter space. Now this object memory is within the ramstage address space. I'm not following how this works. Oh. I see there are other CLs. I think the direction of intermixing cache-as-ram w/ c code is ripe for problems -- just like before.

The assumption is that CAR is torn down and that caching is disabled while the MTRR are set up. Disabling CAR is better done in assembly and without any stack usage to not make any assumptions on the caching that then set up. Setting up new MTRRs after that however does not need to be done in assembly. It's much easier to do this in C code: https://review.coreboot.org/c/coreboot/+/54299/3
You then don't need complicated code pushing data to the postcar stack in a format that has to be kept in sync with how the assembly code treats it.