[coreboot-gerrit] Change in coreboot[master]: cpu/intel/xeonsp: Cache BIOS SPI region

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39050 )

Change subject: cpu/intel/xeonsp: Cache BIOS SPI region
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Patch Set 2: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/39050/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39050/2//COMMIT_MSG@10 
PS2, Line 10: This seems to be an undocumented requirement
            : for FSP-M to function correctly.
AFAIK, it is a documented requirement of the MRC (Memory Reference Code).

I think FSP-M also does QPI/UPI init. Performing any flash accesses while initializing QPI does not seem to be a good idea.