Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47258 )
Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS ......................................................................
mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will select ways for eviction & non-eviction. TGL will have to switch back to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) & IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood.
Bug=b:171601324 BRANCH=volteer Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.
Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47258 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Shreesh Chhabbi: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index b276fb9..f1ac774 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -23,7 +23,8 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select USE_CAR_NEM_ENHANCED_V2 if !INTEL_CAR_NEM + select USE_CAR_NEM_ENHANCED_V1 if !INTEL_CAR_NEM + select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC