[coreboot-gerrit] Change in coreboot[master]: amd/picasso/verstage: replace rsa accel with modexp

[Eric Peers (Code Review)]

Eric Peers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45987 )

Change subject: amd/picasso/verstage: replace rsa accel with modexp
......................................................................

Patch Set 5:
> Patch Set 5:
>
> st

Not sure why I got an "st" on this. Apologies. I think Angel is commenting that we are doing some byte swizzling and that the preferred implementation is to treat the buffer in both a: the right size, and b: not swizzle if possible. So we should explore this in a follow up bug with AMD on refining the svc call.

Angel to agree/disagree.