Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72648 )
Change subject: mb/google/brya: Skip locking for GPP_F14 GPIO ......................................................................
mb/google/brya: Skip locking for GPP_F14 GPIO
This is regarding issues observed on multiple Brya and Nissa variant such as Skolas and Nivviks. Issue is that once coreboot sets GPE_EN bit for the GPIO pin and locks it, kernel is not able to change the control bit. Hence kernel is not able to control the IRQ on the pin when required.
This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking")
This patch skips the locking for GPP_F14 to allow kernel to configure it later during reboot or shutdown as required.
BUG=b:254064671 BRANCH=None TEST=Shutdown works on Skolas and Brya board with the patch.
Signed-off-by: Maulik Vaghela maulikvaghela@google.com Change-Id: I7e4a6ac4668028bcd5fa400b9aa8eccf36a79620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72648 Reviewed-by: Caveh Jalali caveh@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 32 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 9e2be67..f3ab850 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -240,7 +240,7 @@ /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG), + PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */