Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 48:
(2 comments)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/d6fbd1ad_bf203206
PS47, Line 48: m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
I think it will have to be initialized to 0xFF (PCIE_CLK_NOT_USED) just like PcieClkSrcUsage is on l […]
Done
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/611fbe65_5cbc0fd2
PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
PCIE_RP_CLK_REQ_UNUSED this can remove since CPU_RP have the CLK_REQ... […]
Done
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