[coreboot-gerrit] Change in coreboot[master]: {nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44924 )

Change subject: {nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)
......................................................................

{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)

Change-Id: I049441dd9074659effc1092dce08224974d60a2c
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44924
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
---
M src/northbridge/intel/haswell/memmap.c
M src/soc/intel/broadwell/memmap.c
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index a86efeb..807ee2a 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -18,7 +18,7 @@
     * 1 MiB alignment.
     */
    uintptr_t tom = pci_read_config32(HOST_BRIDGE, TSEG);
-	return tom & ~((1 << 20) - 1);
+	return ALIGN_DOWN(tom, 1 * MiB);
 }

void *cbmem_top_chipset(void)
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index bada5fd..4673cce 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -18,7 +18,7 @@
     * must be calculated from the size in MiB in bits 11:4.
     */
    uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR);
-	uintptr_t tom = dpr & ~((1 << 20) - 1);
+	uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB);

/* Subtract DMA Protected Range size if enabled */
    if (dpr & DPR_EPM)