[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x/pcie.c: Drop dead code

[Michael Niewöhner (Code Review)]

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43216 )

Change subject: sb/intel/bd82x6x/pcie.c: Drop dead code
......................................................................

sb/intel/bd82x6x/pcie.c: Drop dead code

This code is not even being build-tested. Drop it before it grows moss.

Change-Id: Icd6b3226814f48c4cdd2c2f879c66cb6847a14e9
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43216
Reviewed-by: HAOUAS Elyes 
Reviewed-by: Frans Hendriks 
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) 
---
M src/southbridge/intel/bd82x6x/pcie.c
1 file changed, 0 insertions(+), 12 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  HAOUAS Elyes: Looks good to me, approved
  Frans Hendriks: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index c381d33..2eff162 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -219,18 +219,6 @@
    pci_update_config16(dev, PCI_BRIDGE_CONTROL,
    		    ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA);

-#ifdef EVEN_MORE_DEBUG
-	u32 reg32;
-	reg32 = pci_read_config32(dev, 0x20);
-	printk(BIOS_SPEW, "    MBL    = 0x%08x\n", reg32);
-	reg32 = pci_read_config32(dev, 0x24);
-	printk(BIOS_SPEW, "    PMBL   = 0x%08x\n", reg32);
-	reg32 = pci_read_config32(dev, 0x28);
-	printk(BIOS_SPEW, "    PMBU32 = 0x%08x\n", reg32);
-	reg32 = pci_read_config32(dev, 0x2c);
-	printk(BIOS_SPEW, "    PMLU32 = 0x%08x\n", reg32);
-#endif
-
    /* Clear errors in status registers. FIXME: Do something? */
    reg16 = pci_read_config16(dev, 0x06);
    //reg16 |= 0xf900;