Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/18952 )
Change subject: soc/intel/common/block: Add Intel common UART code ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/#/c/18952/2/src/soc/intel/common/block/uart/uart... File src/soc/intel/common/block/uart/uart.c:
Line 39: tmp = read32(base + UART_CLK);
I really don't think we should be doing a read modify write. If the values
Okay.Revised for direct write since registers are getting programmed for first time post reset.
PS2, Line 40: N_VAL
These are not very descriptive w.r.t. to the global namespace of the pre-pr
Done.
Line 41: UART_CLK_EN | UART_CLK_UPDATE;
I see skylake is doing this in one full swoop. Is that appropriate for all?
revised to program n and m values with clock update flag and then enabling the clock on next write