Attention is currently required from: Jamie Ryu, Wonkyu Kim, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63198 )
Change subject: soc/intel/common: implement ioc driver ......................................................................
Patch Set 5:
(9 comments)
File src/soc/intel/common/block/include/intelblocks/ioc.h:
https://review.coreboot.org/c/coreboot/+/63198/comment/455dc1de_7542f64e PS5, Line 12: /* nit: Add space after comment beginning
File src/soc/intel/common/block/include/intelblocks/ioc_reg.h:
https://review.coreboot.org/c/coreboot/+/63198/comment/21a944aa_e476ce23 PS5, Line 7: A Please use lowercase for hex
https://review.coreboot.org/c/coreboot/+/63198/comment/c41ef23e_1f04c80a PS5, Line 8: C Ditto
https://review.coreboot.org/c/coreboot/+/63198/comment/cfef4ac2_a913b552 PS5, Line 13: FFE Ditto
https://review.coreboot.org/c/coreboot/+/63198/comment/39aa38dc_e6f6669e PS5, Line 14: A7C Ditto
https://review.coreboot.org/c/coreboot/+/63198/comment/9124f2cc_a7d10b42 PS5, Line 15: A Ditto
File src/soc/intel/common/block/smbus/tco.c:
https://review.coreboot.org/c/coreboot/+/63198/comment/58ffa76e_0fb28332 PS5, Line 126: " Remove stray "
File src/soc/intel/common/pch/lockdown/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63198/comment/154c9cb2_091a5f75 PS5, Line 31: if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOC)) As per the coding style, this should have braces: https://doc.coreboot.org/contributing/coding_style.html#placing-braces-and-s...
This does not apply if only one branch of a conditional statement is a single statement; in the latter case use braces in both branches:
https://review.coreboot.org/c/coreboot/+/63198/comment/59b48d46_7cc26683 PS5, Line 35: /* : * GCS reg of DMI : * : * When set, prevents GCS.BBS from being changed : * GCS.BBS: (Boot BIOS Strap) This field determines the destination : * of accesses to the BIOS memory range. : * Bits Description : * "0b": SPI : * "1b": LPC/eSPI : */ : pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); : : /* : * Set Secure Register Lock (SRL) bit in DMI control register to lock : * DMI configuration. : */ Please indent the comments accordingly as well.