Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47964 )
Change subject: [WIP] arch/x86: Clean up bootblock assembly ......................................................................
[WIP] arch/x86: Clean up bootblock assembly
We hae identical gdtptr16 and gdtptr. The reference in gdtptr_offset calculation is not accounted for when considering --gc-sections, so to support linking gdt_init.S separately add dummy use of gdtptr symbol.
Realmode execution already accessed gdt that was located outside [_start16bit,_estart16bit] region. Remove latter symbol as the former was not really a start of region, but entry point symbol.
With the romcc bootblock solution, entry32.inc may have been linked into romstage once.
Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/bootblock.ld M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/32bit/entry32.inc M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld 4 files changed, 6 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/47964/1
diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index ff7bb62..4a3dbb9 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-gdtptr16_offset = gdtptr16 & 0xffff; +gdtptr_offset = gdtptr & 0xffff; nullidt_offset = nullidt & 0xffff;
/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 13d12be..2665cc6 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -108,7 +108,7 @@ movw $nullidt_offset, %bx subw %ax, %bx lidt %cs:(%bx) - movw $gdtptr16_offset, %bx + movw $gdtptr_offset, %bx subw %ax, %bx lgdtl %cs:(%bx)
@@ -127,11 +127,8 @@ * The gdt is defined in entry32.inc, it has a 4 Gb code segment * at 0x08, and a 4 GB data segment at 0x10; */ -.align 4 -.globl gdtptr16 -gdtptr16: - .word gdt_end - gdt -1 /* compute the table limit */ - .long gdt /* we know the offset */ +__gdtptr: + .long gdtptr
.align 4 .globl nullidt @@ -139,7 +136,3 @@ .word 0 /* limit */ .long 0 .word 0 - -.globl _estart16bit -_estart16bit: - .code32 diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index be67b53..8509448 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -8,29 +8,11 @@
.code32 /* - * When we come here we are in protected mode. We expand - * the stack and copies the data segment from ROM to the - * memory. - * - * After that, we call the chipset bootstrap routine that - * does what is left of the chipset initialization. - * + * When we come here we are in protected mode. * NOTE aligned to 4 so that we are sure that the prefetch * cache will be reloaded. - * - * In the bootblock there is already a ljmp to __protected_start and - * the reset vector jumps to symbol _start16bit in entry16.inc from - * the reset vectors's symbol which is _start. Therefore, don't - * expose the _start symbol for bootblock. */ .align 4 -#if !ENV_BOOTBLOCK -.globl _start -_start: -#endif - - lgdt %cs:gdtptr - ljmp $ROM_CODE_SEG, $__protected_start
__protected_start: /* Save the BIST value */ diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 369d431..c2b37f8 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -98,7 +98,7 @@
#if ENV_BOOTBLOCK
-gdtptr16_offset = gdtptr16 & 0xffff; +gdtptr_offset = gdtptr & 0xffff; nullidt_offset = nullidt & 0xffff;
SECTIONS {