[coreboot-gerrit] Change in coreboot[master]: WIP: Add configurable ramstage support for minimal PCI scanning

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36221 )

Change subject: WIP: Add configurable ramstage support for minimal PCI scanning
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Patch Set 14:
> Patch Set 14:
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> So have we gone from wanting to not assign resources for certain devices to not assigning resources for almost all devices unless someone explicitly changes the code?

i still believe our goal should be "wanting to not assign resources for certain devices" and that we should control using some static keyword what Ron has made like "mandatory". like in my experiment earlier. In order to boot to payload we need only below devices

1. Host Bridge 0:0:0 to create basic memory mark as RAM
2. IGD if we are in !NORMAL_MODE
3. Block Device like eMMC/NVME (incase of NVME we might need to look for PCIE root port, but that is also fixed should we look for 0:1c:0 or 0:1d:0 and in case of eMMC we anyway have dedicated PCI B:D:F)

Just by allocating resources dynamically to these 3 devices we could boot to OS happily. I believe that was the agenda when we say configurable ramstage option enable. Isn't it ?