6 Dec
2021
6 Dec
'21
10:45 a.m.
Attention is currently required from: Nico Huber, Furquan Shaikh, Paul Menzel, Meera Ravindranath, Subrata Banik, Ronak Kanabar, Patrick Rudolph. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52730 )
Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64 ......................................................................
Patch Set 8: Code-Review+1
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe
Gerrit-Change-Number: 52730
Gerrit-PatchSet: 8
Gerrit-Owner: Meera Ravindranath meera.ravindranath@intel.com
Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com
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Gerrit-Comment-Date: Mon, 06 Dec 2021 18:45:37 +0000
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