[coreboot-gerrit] Change in coreboot[master]: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM conf...

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46652 )

Change subject: Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration"
......................................................................

Revert "mb/google/dedede: Add mainboard acpi support for GPIO PM configuration"

This reverts commit 214c719eed83967b8f0564feca65eebb3d83f5bc.
CB:45857 overrides the GPIO PM configuration if Cr50 does not support
long interrupt pulse width. More recent Cr50 Firmware versions support
long pulse width and hence the GPIO PM can take the default
configuration.

BUG=None
TEST=Build and boot Drawlat to OS. Ensured that 200 iterations of
suspend/resume sequence, warm and cold reboot cycles each are
successful.

Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a
Signed-off-by: Karthikeyan Ramasubramanian 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46652
Tested-by: build bot (Jenkins) 
Reviewed-by: Justin TerAvest 
Reviewed-by: Angel Pons 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Evan Green 
---
D src/mainboard/google/dedede/acpi/mainboard.asl
M src/mainboard/google/dedede/dsdt.asl
2 files changed, 0 insertions(+), 52 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Justin TerAvest: Looks good to me, approved
  Evan Green: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/google/dedede/acpi/mainboard.asl b/src/mainboard/google/dedede/acpi/mainboard.asl
deleted file mode 100644
index 0fa27da..0000000
--- a/src/mainboard/google/dedede/acpi/mainboard.asl
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <intelblocks/gpio.h>
-#include <soc/gpio_soc_defs.h>
-
-Method (PGPM, 1, Serialized)
-{
-	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
-	{
-		_SB.PCI0.CGPM (Local0, Arg0)
-	}
-}
-
-/*
- * Method called from _PTS prior to system sleep state entry
- * Enables dynamic clock gating for all 5 GPIO communities
- */
-Method (MPTS, 1, Serialized)
-{
-	PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
-}
-
-/*
- * Method called from _WAK prior to system sleep state wakeup
- * Disables dynamic clock gating for all 5 GPIO communities
- */
-Method (MWAK, 1, Serialized)
-{
-	PGPM (0)
-}
-
-/*
- * S0ix Entry/Exit Notifications
- * Called from _SB.LPID._DSM
- */
-Method (MS0X, 1, Serialized)
-{
-	If (Arg0 == 1) {
-		/* S0ix Entry */
-		PGPM (MISCCFG_ENABLE_GPIO_PM_CONFIG)
-	} Else {
-		/* S0ix Exit */
-		PGPM (0)
-	}
-}
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl
index 1698c88..39cc25e 100644
--- a/src/mainboard/google/dedede/dsdt.asl
+++ b/src/mainboard/google/dedede/dsdt.asl
@@ -27,9 +27,6 @@
    		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
    		#include <soc/intel/jasperlake/acpi/southbridge.asl>
    	}
-
-		/* Mainboard hooks */
-		#include "acpi/mainboard.asl"
    }

#if CONFIG(VARIANT_HAS_CAMERA_ACPI)
@@ -37,10 +34,6 @@
    #include <variant/acpi/camera.asl>
 #endif

-	/* Include Low power idle table for a short term workaround to enable
-	   S0ix. Once cr50 pulse width is fixed, this can be removed. */
-	#include <soc/intel/common/acpi/lpit.asl>
-
    /* Chrome OS specific */
    #include <vendorcode/google/chromeos/acpi/chromeos.asl>