Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32176 )
Change subject: mb/google/hatch: Update GPIO settings ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/32176/6/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/baseboard/gpio.c:
https://review.coreboot.org/#/c/32176/6/src/mainboard/google/hatch/variants/... PS6, Line 109: /* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */ : PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
Were you able to try this out?
Sorry Furquan for late response. SerialIoSpi1CsEnable is not checked while setting GPIO native function in FSP. Setting it to 0 or 1 does not affect SPI1 CS0 being set to NF1. However, this UPD is checked to set the SPI CS polarity. I would recommend setting this GPIO pin in coreboot to align with the FSP settings.