1 comment:
File src/mainboard/google/hatch/variants/baseboard/gpio.c:
/* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
Were you able to try this out?
Sorry Furquan for late response. SerialIoSpi1CsEnable is not checked while setting GPIO native function in FSP. Setting it to 0 or 1 does not affect SPI1 CS0 being set to NF1. However, this UPD is checked to set the SPI CS polarity.
I would recommend setting this GPIO pin in coreboot to align with the FSP settings.
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