[coreboot-gerrit] Change in coreboot[master]: device/pci_device: Map big PCI bars above 4 GiB

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46617 )

Change subject: device/pci_device: Map big PCI bars above 4 GiB
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device/pci_device: Map big PCI bars above 4 GiB

Map BARs bigger than 4GiB to memory space above 4GiB.
FIXME: This should probably go into the resource allocator.

Required for Nvidia NV100, which has a 32GiB BAR for accessing the VRAM.

Change-Id: Ief34e5bc1c2133ba7380acc9468d4e1042e6e100
Signed-off-by: Patrick Rudolph 
---
M src/device/pci_device.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46617/1

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 3623c3b..36af0d9 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -178,6 +178,9 @@
    		/* 64bit limit. */
    		resource->limit = 0xffffffffffffffffULL;
    		resource->flags |= IORESOURCE_PCI64;
+
+			if (resource->size >= 0x100000000ULL)
+				resource->flags |= IORESOURCE_ABOVE_4G;
    	} else {
    		/* Invalid value. */
    		printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);