[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Log CSE FW Status Registers before triggering recovery

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43537 )

Change subject: soc/intel/common: Log CSE FW Status Registers before triggering recovery
......................................................................

soc/intel/common: Log CSE FW Status Registers before triggering recovery

The patch logs CSE Firmware Status Registers(FWSTS1, FWSTS2 & FWSTS3)
before triggering recovery to help debugging.

BUG=b:159962240
Test=Verified on hatch

Signed-off-by: Sridhar Siricilla 
Change-Id: I90e9f5897408bfc37a69cf0bb23bff18a146b9e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43537
Reviewed-by: Angel Pons 
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index a12f2d0..ff489af 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -153,8 +153,17 @@
    struct cse_bp_info bp_info;
 } __packed;

+static void cse_log_status_registers(void)
+{
+	printk(BIOS_DEBUG, "cse_lite: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x "
+			"HFSTS3: 0x%x\n", me_read_config32(PCI_ME_HFSTS1),
+			me_read_config32(PCI_ME_HFSTS2), me_read_config32(PCI_ME_HFSTS3));
+}
+
 static void cse_trigger_recovery(uint8_t rec_sub_code)
 {
+	/* Log CSE Firmware Status Registers to help debugging */
+	cse_log_status_registers();
    if (CONFIG(VBOOT)) {
    	struct vb2_context *ctx;
    	ctx = vboot_get_context();