Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10885
-gerrit
commit ad13d86711020b75101959c3cd0cd2169801e82c Author: Martin Roth gaumless@gmail.com Date: Sat Jul 11 13:42:54 2015 -0600
Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()
Kconfigs symbols of type bool are always defined, and can be tested with the IS_ENABLED() macro.
symbol type except string.
Change-Id: Ic4ba79f519ee2a53d39c10859bbfa9c32015b19d Signed-off-by: Martin Roth gaumless@gmail.com --- src/arch/arm64/armv8/bootblock_simple.c | 2 +- src/arch/riscv/bootblock_simple.c | 2 +- src/cpu/x86/mtrr/earlymtrr.c | 2 +- src/include/device/dram/ddr3.h | 2 +- src/include/device/early_smbus.h | 2 +- src/lib/ramstage.ld | 2 +- src/lib/rmodule.ld | 2 +- src/northbridge/intel/haswell/gma.c | 2 +- src/soc/broadcom/cygnus/ddr_init.c | 38 +++++++++++++++---------------- src/soc/broadcom/cygnus/ddr_init_table.c | 2 +- src/southbridge/intel/i82801ix/i82801ix.h | 2 +- 11 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/src/arch/arm64/armv8/bootblock_simple.c b/src/arch/arm64/armv8/bootblock_simple.c index 5e00890..6cb55e6 100644 --- a/src/arch/arm64/armv8/bootblock_simple.c +++ b/src/arch/arm64/armv8/bootblock_simple.c @@ -55,7 +55,7 @@ void main(void) //bootblock_mainboard_init(); }
-#ifdef CONFIG_BOOTBLOCK_CONSOLE +#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE) console_init(); exception_init(); #endif diff --git a/src/arch/riscv/bootblock_simple.c b/src/arch/riscv/bootblock_simple.c index 50cd90d..a10cdaf 100644 --- a/src/arch/riscv/bootblock_simple.c +++ b/src/arch/riscv/bootblock_simple.c @@ -56,7 +56,7 @@ void main(void) //bootblock_mainboard_init(); }
-#ifdef CONFIG_BOOTBLOCK_CONSOLE +#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE) console_init(); exception_init(); #endif diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 0471a9e..3db676b 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -19,7 +19,7 @@ void set_var_mtrr( wrmsr(MTRRphysMask_MSR(reg), maskm); }
-#if !defined(CONFIG_CACHE_AS_RAM) || !CONFIG_CACHE_AS_RAM +#if !IS_ENABLED(CONFIG_CACHE_AS_RAM) static void cache_ramstage(void) { /* Enable caching for lower 1MB and ram stage using variable mtrr */ diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 295ea25..7f969b3 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -55,7 +55,7 @@ * disabled. * @{ */ -#if defined(CONFIG_DEBUG_RAM_SETUP) && (CONFIG_DEBUG_RAM_SETUP) +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) #define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) #else #define printram(x, ...) diff --git a/src/include/device/early_smbus.h b/src/include/device/early_smbus.h index 437a569..1da3f07 100644 --- a/src/include/device/early_smbus.h +++ b/src/include/device/early_smbus.h @@ -55,7 +55,7 @@ /** * \brief printk macro for SMBus debugging */ -#if defined(CONFIG_DEBUG_SMBUS) && (CONFIG_DEBUG_SMBUS) +#if IS_ENABLED(CONFIG_DEBUG_SMBUS) #define printsmbus(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) #else #define printsmbus(x, ...) diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld index 402f495..432df40 100644 --- a/src/lib/ramstage.ld +++ b/src/lib/ramstage.ld @@ -34,7 +34,7 @@ _etext = .; } : to_load
-#ifdef CONFIG_COVERAGE +#if IS_ENABLED(CONFIG_COVERAGE) .ctors : { . = ALIGN(0x100); __CTOR_LIST__ = .; diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 0e9c880..e6b4da7 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -30,7 +30,7 @@ SECTIONS /* C read-only data. */ . = ALIGN(16);
-#ifdef CONFIG_COVERAGE +#if IS_ENABLED(CONFIG_COVERAGE) __CTOR_LIST__ = .; *(.ctors); LONG(0); diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 21a285c..3c50a17 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -460,7 +460,7 @@ static void gma_func0_init(struct device *dev) dp.panel_power_up_delay = conf->gpu_panel_power_up_delay; dp.panel_power_cycle_delay = conf->gpu_panel_power_cycle_delay;
-#ifdef CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) init_fb = developer_mode_enabled() || recovery_mode_enabled(); #endif lightup_ok = panel_lightup(&dp, init_fb); diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index a8369ec..f885cec 100755 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -45,7 +45,7 @@ extern unsigned int ddr3_init_tab_1066[]; #define CONFIG_DRAM_FREQ 667 extern unsigned int ddr3_init_tab_1333[]; #endif -#ifdef CONFIG_CYGNUS_DDR800 +#if IS_ENABLED(CONFIG_CYGNUS_DDR800) #define CONFIG_DRAM_FREQ 800 extern unsigned int ddr3_init_tab_1600[]; #endif @@ -64,7 +64,7 @@ int cygnus_phy_powerup(void); void ddr_init2(void); void PRE_SRX(void);
-#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) void PRE_SRX(void) { uint32_t readvalue = 0; @@ -281,7 +281,7 @@ void iproc_clear_ecc_syndrome(void) } #endif
-#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit) { uint32_t ndiv, mdiv, pdiv, ddrclk, data; @@ -306,7 +306,7 @@ uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit)
#endif
-#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
int cygnus_phy_powerup(void) { @@ -1187,7 +1187,7 @@ static int clear_ddr(uint32_t offset, uint32_t size) extern void restore_shmoo_config(and28_shmoo_config_param_t *shmoo_control_para); #endif
-#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) static int simple_ddr_crc32_check(void) { return 0; @@ -1226,7 +1226,7 @@ void ddr_init2(void) uint32_t status, sku_id, ddr_clk, dev_id = 0; uint32_t unit = 0; uint32_t skip_shmoo = 0; -#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) uint32_t pwrctli0 = reg32_read((volatile uint32_t *)IHOST_SCU_POWER_STATUS) & 0x3; skip_shmoo = reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG) & 0x1;
@@ -1239,22 +1239,22 @@ void ddr_init2(void) skip_shmoo = 1; reg32_write((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL, reg32_read((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL)| 0x1); } -#endif /* defined(CONFIG_SOC_BROADCOM_CYGNUS) */ +#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */
dev_id = dev_id; -#ifdef CONFIG_SOC_BROADCOM_CYGNUS +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) and28_shmoo_dram_info_t sdi; and28_shmoo_config_param_t config_param; #endif
-#ifndef CONFIG_SOC_BROADCOM_CYGNUS +#if !IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) dev_id = (reg32_read((volatile uint32_t *)ChipcommonA_ChipID)) & 0x0000ffff; #else dev_id = 0x5800; cygnus_phy_powerup(); #endif
-#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 8) & 0x0f; #else sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 2) & 0x03; @@ -1279,7 +1279,7 @@ void ddr_init2(void) goto done; } printk(BIOS_INFO, "DDR type: DDR%d\n", (ddr_type == 1)? 3 : 4); -#elif defined(CONFIG_SOC_BROADCOM_CYGNUS) +#elif IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) ddr_type = 1; #else ddr_type = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x1; @@ -1337,7 +1337,7 @@ void ddr_init2(void) } #endif /* defined(CONFIG_IPROC_P7) */
-#if defined(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) /* Get the DDR S1 and S2 out of reset */ reg32_write((volatile uint32_t *)DDR_S1_IDM_RESET_CONTROL, 0); reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0); @@ -1357,7 +1357,7 @@ void ddr_init2(void) reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0); /* Set the ddr_ck to 400 MHz, 2x memc clock */ reg32_write_masked((volatile uint32_t *)DDR_S1_IDM_IO_CONTROL_DIRECT, 0xfff << 16, /*ddr_clk*/ 0x190 << 16); -#endif /* defined(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) */ +#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) */
#if defined(CONFIG_IPROC_P7) if (is_ddr_32bit()) { @@ -1398,7 +1398,7 @@ void ddr_init2(void) return; }
-#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) if(!skip_shmoo) { printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_dram_info_set\n"); @@ -1433,7 +1433,7 @@ void ddr_init2(void) #error "DRAM config is not set" #endif
-#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) if(!skip_shmoo) { printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_phy_init\n"); @@ -1481,7 +1481,7 @@ void ddr_init2(void) ddr_init_regs(ddr3_init_tab_1333); break; #endif -#if (defined(CONFIG_DDR750) || defined(CONFIG_CYGNUS_DDR800)) +#if (defined(CONFIG_DDR750) || IS_ENABLED(CONFIG_CYGNUS_DDR800)) case 750: case 800: ddr_init_regs(ddr3_init_tab_1600); @@ -1514,7 +1514,7 @@ void ddr_init2(void) /* Start the DDR */ reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_00, 0x01);
-#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) if(!skip_shmoo) { while(!(reg32_read((volatile uint32_t *)DDR_DENALI_CTL_175) & 0x100)); @@ -1605,7 +1605,7 @@ void ddr_init2(void)
//dump_phy_regs();
-#if defined(CONFIG_SOC_BROADCOM_CYGNUS) +#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) /* SRX */ if(skip_shmoo) { @@ -1652,7 +1652,7 @@ wakeup: "ldr r5, [r3]\n" "mov lr, #0\n" "mov pc, r5\n"); -#endif /* defined(CONFIG_SOC_BROADCOM_CYGNUS) */ +#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */
done: /* Reclaim everything we have previously allocated for temporary usage. */ diff --git a/src/soc/broadcom/cygnus/ddr_init_table.c b/src/soc/broadcom/cygnus/ddr_init_table.c index d925895..7c8a89f 100644 --- a/src/soc/broadcom/cygnus/ddr_init_table.c +++ b/src/soc/broadcom/cygnus/ddr_init_table.c @@ -1488,7 +1488,7 @@ const unsigned int ddr3_init_tab_1333[] = { }; #endif
-#ifdef CONFIG_CYGNUS_DDR800 +#if IS_ENABLED(CONFIG_CYGNUS_DDR800) const unsigned int ddr3_init_tab_1600[] = { 14, 0x01000000, 36, 0x0a140a0a, diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index adf81cc..1793ead 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -35,7 +35,7 @@ #define DEFAULT_RCBA 0xfed1c000 #endif
-#ifdef CONFIG_BOARD_EMULATION_QEMU_X86_Q35 +#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) /* * Qemu has the fw_cfg interface at 0x510. Move the pmbase to a * non-conflicting address. No need to worry about speedstep, it