Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86270?usp=email )
Change subject: soc/amd/glinda/chipset.cb: Enable gpp_bridge_[a/b/c] by default ......................................................................
soc/amd/glinda/chipset.cb: Enable gpp_bridge_[a/b/c] by default
TODO justification
Change-Id: Id28a29481f9a1bc570e47a9cb75613d3621b0d44 Signed-off-by: Maximilian Brune maximilian.brune@9elements.com --- M src/soc/amd/glinda/chipset.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/86270/1
diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index f328797..a76be1a 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -32,7 +32,7 @@ device pci 03.6 alias gpp_bridge_3_6 off ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy device function, do not disable - device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + device pci 08.1 alias gpp_bridge_a on # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) @@ -56,13 +56,13 @@ device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end
- device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B + device pci 08.2 alias gpp_bridge_b on # Internal GPP Bridge 1 to Bus B ops amd_internal_pcie_gpp_ops device pci 0.0 on end # dummy, do not disable device pci 0.1 alias npu off end # Neural Processing Unit (NPU) end
- device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops
device pci 0.0 alias xhci_0 off