Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin.
Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )
Change subject: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes ......................................................................
Patch Set 8:
(2 comments)
Patchset:
PS8: Now is when you need that extra SPI flash chip and working coreboot copy and a couple leap of faith - I just posted a complete implementation. Setting pciex16_3_bandwidth between 0 and 1 should not trigger a IFD reflash and you can play with them. Let me know how it works, now that the key logic is now in ramstage.
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/dbf021c9_f82a2d80?usp... : PS7, Line 104: 0x40
Let Setup = /sys/firmware/efi/efivars/Setup-ec87d643-eba4-4bb5-a1e5-3f3e36b20da9 , my result is: […]
So efivarfs does prepend the 4-byte attributes to EFI variables.
Looks like whatever logic around PCIEX1_2_NOT_PRESENT failed to set the GPIO lines at all when a card is present, and put the GPIOs in that invalid state.
Great to hear that x2 actually works.
And according to owners manual, the values 0-2 represents Auto, x4, x1 respectively, which is the question I was trying to answer.