Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5493
-gerrit
commit 0a159b2dc32c593a77fecdd01c19168b23734169 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Sat Apr 12 21:57:18 2014 -0500
cpu/amd/agesa/family15tn: Add initial support for SMM mode
This is the minimal setup needed to be able to execute SMI handlers. Only support for ASEG handlers is added, which should be sufficient for Trinity (up to 4 cores).
There are a few hacks which need to be introduced in generic code in order to make this work properly, but these hacks are self-contained. They are a not a result of any special needs of this CPU, but rather from a poorly designed infrastructure. Comments are added to explain how such code could be refactored in the future.
Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6 Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/cpu/amd/agesa/family15tn/Makefile.inc | 1 + src/cpu/amd/agesa/family15tn/model_15_init.c | 14 ++++++++++++++ src/cpu/x86/smm/smmhandler.S | 8 ++++++++ src/cpu/x86/smm/smmrelocate.S | 3 ++- src/include/cpu/amd/amdfam15.h | 2 ++ 5 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 372113e..a447044 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -457,6 +457,7 @@ romstage-y += $(agesa_lib_src) ramstage-y += $(agesa_lib_src)
subdirs-y += ../../mtrr +subdirs-y += ../../smm subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic subdirs-y += ../../../x86/cache diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index f396201..fd4720d 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -19,6 +19,7 @@
#include <console/console.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/amd/mtrr.h> #include <device/device.h> #include <string.h> @@ -110,6 +111,19 @@ static void model_15_init(device_t dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr);
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + printk(BIOS_DEBUG, "Initializing SMM for CPU %u\n", cpu_info()->index); + /* Set SMM base address for this CPU */ + msr = rdmsr(MSR_SMM_BASE); + msr.lo = SMM_BASE - (cpu_info()->index * 0x400); + printk(BIOS_DEBUG, "SMM basin 0x%x 0x%x\n", msr.hi, msr.lo); + wrmsr(MSR_SMM_BASE, msr); + + /* Enable the SMM memory window */ + msr = rdmsr(MSR_SMM_MASK); + msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ + wrmsr(MSR_SMM_MASK, msr); + }
/* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 774088e..484b643 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -105,6 +105,14 @@ smm_handler_start: movl (%esi), %ecx shr $24, %ecx
+ /* This is an ugly hack, and we should find a way to read the CPU index + * without relying on the LAPIC ID. + */ +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) + /* LAPIC IDs start from 0x10; map that to the proper core index */ + subl $0x10, %ecx +#endif + /* calculate stack offset by multiplying the APIC ID * by 1024 (0x400), and save that offset in ebp. */ diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 71f74e7..bdc9771 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -23,7 +23,8 @@ #define __PRE_RAM__
/* On AMD's platforms we can set SMBASE by writing an MSR */ -#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 +#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 \ + && !CONFIG_CPU_AMD_AGESA_FAMILY15_TN
// FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 0c2cf7b..66c0175 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -23,6 +23,8 @@ #include <cpu/x86/msr.h>
#define MCI_STATUS 0x00000401 +#define MSR_SMM_BASE 0xc0010111 +#define MSR_SMM_MASK 0xC0010113 #define HWCR_MSR 0xC0010015 #define NB_CFG_MSR 0xC001001f